• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 334 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Query on FSYNC Peripheral

Justin Antony G
Intellectual 775 points

Hi,

I have few queries regarding details explained at "http://processors.wiki.ti.com/index.php/FSYNC#Frame_sync_configuration.2C_vConfigFsync.28.29"

"4 chips tick for Protocol Encoder CPRI data construction" and "8400 chips strobe – Protocol Encoder frame synchronization strobe" : Is this mode for UL traffic (AIF to DSP) or for DL Traffic (DSP to AIF)?

"8 chips tick for EDMA inbound data transfer" : Is it one EDMA event per link or one single event for all 6 AIF links?

Regards,

Justin

  • 0
    TI__Expert 4740 points

    Hi Justin,

    I'm Albert Bae who is supporting AIF in TI.

    we have 4 chip duration periodic event for Egress EDMA data transfer and one PE frame preparation signal every frame time to make PE always active.

    these events are mainly used for DL traffic.

    8 chip event for Inbound EDMA is used for UL traffic and each link should have it's own event because RP3 timing could be different for each link.

    Hope this could help to you. if you have additional detail question, please submit SR or send an email directly to me. (a-bae@ti.com)

     

    Regards,

    Albert