Other Parts Discussed in Thread: AM5728
AM5728 GPMC is connected to a FPGA using a multiplexed address/data lines (16 bit wide) to implement an array of I/O registers. The GPMC runs at 266 MHz internally and the GPMC_CLK divided by 4 is an input to FPGA. The FPGA has it's own internal clock of a different frequency (250MHz) and together with GPMC_CLK (66 MHz) detects when an access starts. FPGA Read or write accesses can be of variable length hence gpmc_wait0 is asserted to indicate the end of the cycle (derived from the internal 250 MHz FPGA clock).
Is the gpmc_wait0 an asynchronous input to AM5728 or it needs to be synchronized externally with gpmc_fclk / gpmc_clk to avoid internal metastability ?
