Part Number: TMS320C5505
Hi TI Experts,
Customer board using C5505 suffers from garbling UART. (It's based on USBSTK5505)
It occurs in 2 out of 10 units.
Environment
・ UART Baudrate 115200
・ CLKIN 18.432MHz
・ PLL 18.432 / 384 * 2500 = 120MHz
When checking the power supply and clock, the following abnormalities were confirmed.
・ The potential of VDDA_PLL drops during UART communication
・ UART Baudrate drops from 115200 to about 105000Hz
Now ANA_LDOO is connected to VDDA_PLL and VDD_ANA.
We think that power supply is bad, so power supply is changed.
ANA_LDOO---VDDA_PLL---VDD_ANA
↓
1.3V---CVDD ---VDDA_PLL---VDD_ANA
Then the operation improved.
Question 1:
Customer board is not booting with SPI and I2C. Is it okay to input 18.432MHz to CLKIN?
Question 2:
Is there any cause for dropping voltage?
Question 3:
Is it OK to connect the power supply for CVDD (1.3V) to VDDA_PLL and VDD_ANA?
Regards,Rei
