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AM4376: AM437x.lds memory sections

Arun Cherian
Intellectual 510 points

Part Number: AM4376

Here is the MEMORY section from AM437x.lds. Looking at the TRM Table 2-1. L3 Memory Map, it seems like the L3OCMC is 256kb? And I couldn't figure out where M3SHUMEM and M3SHDMEM maps from. Any help appreciated. Thanks!

MEMORY
{

SRAM : o = 0x402F0000, l = 0x00010000 /* 64kB internal SRAM */
L3OCMC0 : o = 0x40300000, l = 0x00010000 /* 64kB L3 OCMC SRAM */
M3SHUMEM : o = 0x44D00000, l = 0x00004000 /* 16kB M3 Shared Unified Code Space */
M3SHDMEM : o = 0x44D80000, l = 0x00002000 /* 8kB M3 Shared Data Memory */
DDR0 : o = 0x80000000, l = 0x80000000 /* 2GB external DDR Bank 0 *

}

  • 0
    Intellectual 510 points

    Also, shouldn't the stack be 8 bytes aligned instead of 4 per ARM Procedure Call Standards (AAPCS)? . = ALIGN(8);

  • 0 in reply to Arun Cherian
    TI__Mastermind 30108 points

    Hi Arun,

    I wasn't able to locate a linker command file in PRSDK 6.3 or 6.1 which has these memory sections. However, I was able to generate this linker command file while creating a SYS/BIOS example project. Is this where you obtained the file?

    L3OCMC0

    You're correct that L3OCMC0 is 256 kB. This can be seen in the AM437x datasheet. Some PRSDK linker command files define a memory region containing all 256 kB of physical memory. In other cases, the memory region is smaller than the entire 256 kB, or the physical memory in split into different memory regions. For example:

    • one region containing all 256 kB: pdk_am437x_1_0_17/packages/ti/starterware/examples/gcc/am43xx.lds
    • one region containing less than 256 kB: pdk_am437x_1_0_17/packages/ti/starterware/examples/gcc/am43xx_boot_ccs.lds
    • more than one region containing 256 kB: processor_sdk_rtos_am437x_6_03_00_106\demos\rtos_template_app\am437x\evmAM437x\A9\template_app\baremetal\am43xx_ddr.lds

    This doesn't mean the physical memory isn't present, but usage of the memory depends on the application. For example, a portion of the memory is reserved for the bootloader (see: http://software-dl.ti.com/processor-sdk-rtos/esd/docs/06_03_00_106/rtos/index_Foundational_Components.html#usage-notes), so code & static data shouldn't be allocated to this region (note this memory can be used as RAM by the application after boot).

    M3SHUMEM & M3SHDMEM

    I don't know why these memory regions are included in the linker command file.

    Stack alignmentI

    I see this is a part of the ARM Procedure Call Standard, Release 2019Q1.1, "Stack constraints at a public interface". I agree it appears the stack should be aligned to an 8-byte boundary, not a 4-byte boundary. I also notice the PRSDK linker command files have the stack aligned to an 8-byte boundary.

    I'm looping in a colleague to comment further if needed.

    Regards,
    Frank

  • 0 in reply to Frank Livingston
    Intellectual 510 points

    Hello Frank

    Is this where you obtained the file? Yes

    My plan is to use the L3OCMC0 to hold a crc table that has CRCs of .text, .data and .bss. And have some code there that runs a DDR memory test on startup.

    Regards,

    Arun

  • 0 in reply to Arun Cherian
    TI__Guru* 96960 points

    Arun,

    Where are you getting the AM437x.lds file from (exact location please)?

    Which AM437x core is this for (CortexA or CortexM)?

    Todd

  • 0 in reply to ToddMullanix
    Intellectual 510 points

    Not sure of the location of the file in the C:/ti directory, this is the linker file that CCS 9.X and 10.X adds to the CCS project when I create a new project in CCS. To see it, create a new HelloWorld CCS project with AM437X as the target. This is for the AM4376 Cortex A