Part Number: AM5708
Tool/software: TI C/C++ Compiler
Tool/software: TI C/C++ Compiler
IDE: CCS studio v 9.1.0.00010
SDK: C:\ti\pdk_am57xx_1_0_15\packages\ti\csl
Core: DSP Core , A15 core
SOC : AM5708
Board : Custom Board with 512MB RAM
I have created bare-metal work space for DSP core and configured the two interrupts Timer using CSL Library.
Timer Interrupt config :
#define TIMER_IRQ_NO (32U)
#define TIMER_IRQ_XBAR_INST_NO CSL_XBAR_INST_DSP1_IRQ_32
#define TIMER_IRQ_XBAR_CPU_ID CSL_XBAR_IRQ_CPU_ID_DSP1
#define TIMER_BASE_ADDRESS SOC_TIMER9_BASE
#define TIMER_CONFIGURE CM_L4PER_TIMER9_CLKCTRL
#define TIMER_IRQ_XBAR_INDEX CSL_XBAR_TIMER9_IRQ
1.Timer is Tested with 125 us interval separately.
2. DSP core is not running if i configure DSP linker Address more than 0x83A00000 (DDR3_DSP: org = 0x83A00000 len = 0x02000000). Kindly anyone help to solve this issue.
The Testing steps and Linker scripts are shared below
1. The DSP core is hanging for below condition
1. Linker Address is more than 0x83A00000 and if i enable the Timer interrupt the board
2. The DSP core is working for below condition
1. Linker Address is range is( 0x80000000 - 0x83A00000) with Timer interrupt and without timer interrupt
2. Linker Address is range is cross the 0x83A00000 the without Timer interrupt only dsp core is running
DSP Linker configuration :
-stack 0x2000 /* SOFTWARE STACK SIZE */
-heap 0x2000 /* HEAP AREA SIZE */
/* SPECIFY THE SYSTEM MEMORY MAP */
MEMORY
{
RST_START: org = 0x00800000 len = 0x0300
IRAM_MEM: org = 0x00800300 len = 0x7c00
MMU_TLB: org = 0x4031C000 len = 0x000004000
DDR3_DSP: org = 0x83A00000 len = 0x02000000 /* 32 MB For DSP Core*/
DDR3_A15: org = 0x90000000 len = 0x0A000000 /* 160 MB For A15 Core*/
DDR3_SM: org= 0x9D000000 len = 0x01000000 /* 16 MB for Shared memory*/
}
/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
SECTIONS
{
.cachetest_ddrbuf > DDR3_DSP
GROUP: load > DDR3_DSP
{
.bss: /* UNINITIALIZED OR ZERO INITIALIZED */
.neardata:
.rodata:
}
BOARD_IO_DELAY_DATA : load > IRAM_MEM
BOARD_IO_DELAY_CODE : load > IRAM_MEM
.csl_vect : load > RST_START
.vects : load > IRAM_MEM
.l2_int : load > IRAM_MEM
.pmIdleFunc : load > IRAM_MEM
.init : load > DDR3_DSP
.cio : load > DDR3_DSP
.text : load > DDR3_DSP /* CODE */
.data : load > DDR3_DSP /* INITIALIZED GLOBAL AND STATIC VARIABLES. */
/* GLOBAL & STATIC VARIABLES. */
RUN_START(bss_start)
RUN_END(bss_end)
.const : load > DDR3_DSP /* GLOBAL CONSTANTS */
.cinit : load > DDR3_DSP
.stack : load > DDR3_DSP /* SOFTWARE SYSTEM STACK */
.far : load > DDR3_DSP
.plt : load > DDR3_DSP
.fardata : load > DDR3_DSP
.switch : load > DDR3_DSP
.my_sect_ddr : load > DDR3_DSP
.sysmem : load > DDR3_DSP
}
