TDA4VMXEVM: Quad ethernet expansion board interfaces

Hi Dave,

Sorry for late reply i was busy with other work.

I managed to download the guide and patch files, but i was unable to successfully apply patch.
Apparently k3-j721e-common-proc-board.dts file from which patch was created and one that is being shipped with PSDKLA differ. For example patch tries to change lines: @@ -863,8 +864,7 @@, but my dts file have only 849 lines, 850 if you include newline at the end. There are also other quarrels in patch but it mainly fails because it is trying to change lines that do not exist:

$ patch -p1 --dry-run -d . < 0001-disable-SERDES0-PCIe0.patch
checking file arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
Hunk #1 succeeded at 786 with fuzz 2 (offset -27 lines).
Hunk #2 FAILED at 864.
Hunk #3 succeeded at 848 with fuzz 2 (offset -66 lines).
1 out of 3 hunks FAILED
checking file arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
Hunk #1 succeeded at 46 (offset -7 lines).

I will continue to do a manual patch, and will let you know how it went. We want to avoid constantly using prebuild binaries and start generating our own so that is why we are not trying the prebuild ones that come with patch files.

We are also curious why we must disable pcie0 on serdes0 in order for eth expansion board to work? We see both of them are connected to serdes0 but each on different lane, pcie0 on lane0 and sgmii2 (connected to eth phy on eth expansion board) on lane1. Should not both of them be able to work?

Or the driving clock for serdes can cause issues, hence sgmii and pcie have different work clocks (125Mhz and 100MHz respectively)?

Regards.
Uros

Uros,

The patch should be working if applied directly with the SDK 6.2 release. Please do let me know more specifics there.

In terms of the SerDes configuration we'll have the more integrated in the upcoming SDK release. For now the patch is required. 

The reason for disabling the PCIe is due to the shared SerDes initialization. While it is a 2-lane SerDes and 1L PCIe can operate concurrently with 1L QSGMII it is required to set up both lanes at the same time. So the exact initialization sequence and dependencies to set up for the two interfaces concurrently is still in work. For now it needs to be an either/or.

Best regards,

Dave

Hi Dave,

I will elaborate steps i took:

First:

After i downloaded the patch files, and started reading the Enable 8 Port Ethernet with Linux in J7 EVM i tried to apply the 0001-disable-SERDES0-PCIe0.patch. Looking in the patch i determined that it needs to be placed in psdkla/board-support/linux-4.19.94+gitAUTOINC+5a23bc00e0-g5a23bc00e0, so i did that and check it with command: $ patch -p1 --dry-run -d . < 0001-disable-SERDES0-PCIe0.patch
But that failed:

checking file arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
Hunk #1 succeeded at 786 with fuzz 2 (offset -27 lines).
Hunk #2 FAILED at 864.
Hunk #3 succeeded at 848 with fuzz 2 (offset -66 lines).
1 out of 3 hunks FAILED
checking file arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
Hunk #1 succeeded at 46 (offset -7 lines).

After that i looked again in patch and saw that lines of hunks that are being changed differ from lines that are in my dts file, and even some hunks. I will attach my dts so you can take a look. Hunks that are adding lines are successful but lines that are being changed fail, for example hunk one changes on line 813:

@@ -813,6 +813,7 @@
    phys = <&serdes0_pcie_link>;
    phy-names = "pcie_phy";
    num-lanes = <1>;
+  status = "disabled";
    };

    &pcie1_rc {

But in my dts i can find similar code on line 803:

&pcie0_rc {
reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie_phy";
};

&pcie1_rc {

And the num parameter is set on line 788:

&pcie0 {
pci-mode = <PCI_MODE_RC>;
num-lanes = <1>;
};

Nonetheless i managed to make changes manually and rebuild the kernel, the build passed and im hoping everything is in order.

Second:

Next step from Enable 8 Port Ethernet with Linux in J7 EVM is to modify pdk\packages\ti\drv\cpsw\cpsw_component.mk and ethfw\apps\app_remoteswitchcfg_server\mcu_2_0\main_tirtos.c, which i did, but i got stuck at following:
The guide tells us "After complete above change, you need to make a new app_remoteswitchcfg_server.xer5f and replace the default
firmware in sd_card/rootfs/lib/firmware." So i looked up where we have "app_remoteswitching_server", and found it in psdkra/ethfw so i figured i need to rebuild ethfw and that failed:

error: errors encountered during linking;
   "/home/rtrk/pm300/sw/ti/psdkra/ethfw/out/J721E/R5F/SYSBIOS/release/app_remot
   eswitchcfg_server.xer5f" not built
concerto/finale.mak:226: recipe for target '/home/rtrk/pm300/sw/ti/psdkra/ethfw/out/J721E/R5F/SYSBIOS/release/app_remoteswitchcfg_server.xer5f' failed

There are a lot of unresolved symbols. I will put complete build output in the attachment.

Regards.
Uros

 1057.attatchment.zip

Hi Dave,

I started debugging the linking errors and concluded that libraries from PDK are missing.

We have rebuild the PDK separately and now all libraries are there and build for ethernet firmware passes.
Patches i manually made are okay, now quad ethernet adapter board is live and linux can access it.

Thank you for your help.

Regards
Uros