McASP AHCLKXCTL clock divider

David,

David Lemon said:

I appear to be feeding the 24MHz aux clk directly through (divide by 1) dispite altering the value in this register, and having the bit enabled to use the AUX clk.   

Are you aware of the reset sequence as specified section 2.4 of the OMAP-L138 McASP User's Guide? If not it would be a good guide to set up the McASP to operate properly.

From the above statement, I'll assume that you are generating the clock to the McASP module via AUXCLK, and that you have the PINMUX registers configured properly since you appear to be getting some sort of clock out of the device. There are a few more registers that need to be configured in addition to the AUXCLK bit. In particular, I would take a look at the Global Control Register  (GBLCTL). You can alternatively use the XGBLCTL register to mask off the bits that affect the Rx side of the McASP.

By default, the AHCLKX Divider is held in reset, and needs to be released during initialization.