AM1705 RMII port timing issue

Roma BHagat said:

1) Timings given in datasheet are final, or are there any updates?

These should be considered as final.

Roma BHagat said:

2) Is Transmit propagation delay time as high as mentioned in datasheet ; 2.5nsec to 13nsec for clock period of 20nsec?

You could interpret this to mean that the receiver will see data one clock cycle after the transmitter has sent the information.  Since the Tx data is not valid until at least 2.5ns after CLKH, it means that the hold-time requirements for the Rx side (2ns) are met for the previous data.  Also, since the Tx data is valid at most 13ns after CLKH, the setup-time requirements for the Rx side (4ns) are met for the next clock cycle.

-Tommy

Hi Tommy,

As per 88E6060 datasheet, setup time requiremnt for RX data (TX from AM1705) is minimum 9.5nsec; however propogation delay of AM1705 is max. 13.5nsec. Delay is with reference to clock edge 1 (rising edge) and setup is check with reference to clock edge2 (rising edge); effective data valid period before clock edge2 is about 7nsec; hence we have setup time violation of about 2.5nsec.

Similarly, when we check hold time requirement TX data (RX for AM1705); we observe hold time violation of around 2nsec (min. delay for 88E6060 outputs is 0nsec as per datasheet).

Pls. clarify.

Thanks,

Roma

Roma,

I see what you are concerned about.  I suppose this is a situation where two devices are not necessarily compatible with each other on paper without some effort.  Do you think that you could route the CLK so that the AM1705 sees the clock transitions about 3ns before the 88E6060?  I think that would close the gap some.

I assume that your application does not have an ethernet PHY in the picture.  If so, the AM1705 can provide the RMII 50MHz reference clock and you just need to provide a longer clock route to the 88E6060.  Also, you can consider running the clock at a slower speed.

-Tommy