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C67x dMAX Performance

Richard Young
Prodigy 190 points

We have an application on a C6727 that appears to be pushing the limits of the dMAX due to our high samples rates serviced by the McASPs.  The answer to the question below is important to understand how much dMAX processing margin we have.

The dMAX's MAX0 and MAX1 units offer the potential for two DMA transfers happening concurrently thereby doubling the throughput of the dMAX.  However, this doubled performance is qualified by the statement that the two units must operate to/from different sources/destinations.  I'd like to understand better the performance of the dMAX unit as a whole under the following particular configuration.

1. MAX0 is transfering data from internal RAM to McASP0 Tx (McASP in TDM mode).

2. MAX1 is transfering data from McASP1 Rx to internal RAM (McASP in TDM mode).

Since these two transfers both involve internal RAM and McASP on their ends, does this completely constrain the whole dMAX performance to that of a single unit?

  • 0
    Prodigy 190 points 
    Well, no answers have been provided to my previous post but we have been able to answer it ourselves by experimenting 
    on our C6727 EVM.  

    Through experiments we first confirmed that the throughput of a single dMAX unit is limited according to the description in 
    section 4 of Spru795d for internal memory to McASP transfers.  To do this we tried transfers from internal memory to a 
    McASP tx port (single serializer, via DMA port) using progressively lower values of SYSCLK2 until tx underrun errors occurred.  
    From that we were able to calculate the number of dMAX cycles taken by the dMAX to service a sync event from the McASP.  
    Our results agreed with Table 4-5.

    Using a similar experimental strategy to that above, we next determined that employing the MAX0 and MAX1 units to service 
    separate McASP transfers (tx on McASP0 and tx on McASP1) gives double the throughput of a single MAX unit even if both 
    MAX0 and MAX1 read from internal memory and write to a McASP port.  This is the hoped for result.