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TDA2P-ACD: Power-up and power down sequences

Vicent Climent14
Intellectual 360 points
Part Number: TDA2P-ACD

Dear TI members,

Your datasheet shows a recommended power up and power down sequencing timings. 

This timing values are the minimum value or maximum value?

So for example, for the power up case, T1 is recommended to be 0.55ms. Is it possible to trigger VDDA_PLL group after that time or should we do it before 0.55ms?

------------------------------------------------------------------

BR,

Vicent Climent

  • 0
    TI__Intellectual 1245 points

    Hi Vincent,

    Considering that you've completed ramping up vdds18v_* group before T1, you can start ramping VDDA_PLL group at any time after T1, but it should be fully ramped before T2.

    Thanks,

    Dian

  • 0 in reply to Dian Iliev
    Intellectual 360 points

    Hi Dian,

    Thx for your quick answer. 

    Then, continuing with VDDA_PLL example. This group should always rise 0.55ms after vdds18v and be operational before 1.1ms. So in VDDA_PLL case, the power up is always constraint to be between T1 and T2 values given in the datasheet (0.55ms to 1.1ms taking vdds as reference). Is that correct? 

    I'm asking because in our current implementation we are fulfilling the groups orders during the power up sequence, but not the time stamps of Note 1.

    Current case:

    • T1 = 4.2ms (VDDA_PLL group)
    • T2 = 5ms  (VDDS_DDR group)
    • T3 = 9.55ms (VDD_CORE group)
    • ...

    As you can see our power-up sequence is currently much slower and relax than the one proposed in the DS. Is this OK from TDA side?

    BR,

    Vicent 

  • 0 in reply to Vicent Climent14
    TI__Intellectual 1245 points

    Hi Vincent,

    In general those are more like approximate times and should not be a problem to maintain some small deviations, as long as you follow the power sequencing.

    However, your times look a lot bigger and you should try to shorten them.

    One thing that pops up on my mind is that holding the device in reset for a long time could be an issue - i.e. In cases where external pull resistors conflict with internal pull resistors, the conflict may create a voltage offset on the associated pins until reset is released and the pad configuration registers are programmed to disable conflicting internal resistors. System initialization software should disable internal resistors as soon as possible for pins with conflicting external resistors to minimize the exposure time to this offset.

    Thanks,

    Dian