TDA4VM: Why Linux information on A72 is sent to MCU Domain

AllenHsu

Intellectual 980 points

Part Number: TDA4VM

Hi,

Currently, our Linux data on A72 is sent to the MCU Domain network interface.

The RJ45 connector as shown below.

This situation is puzzling me.

Referring to the figure below, I think the Linux data on A72 will only come in and out from CPSW 9G.

Unless the Ethernet Driver 9G in the mcu domain will collect the CPSW 9G data, and then pass the data to the Ethernet Driver 2G to send it out.

Another possible situation is that the RJ45 connector above is currently set to connect to CPSW 9G.

over 5 years ago

0 Dave Bell over 5 years ago

TI__Genius 14680 points

Allen,

Architecturally, while the CPSW2G is part of the MCUSS and can be firewalled to operate exclusively in this domain, it can also be accessible to the A72s. This is the current default configuration, and the TI Processor SDK has the MCU CPSW2g driver enabled by default. Please refer to http://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/latest/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/K3_CPSW2g.html for details.

The CPSW2G is not going through the CPSW9G and Ethernet Firmware, but is directly managed by the Linux network drivers.

Best regards,

Dave

0 AllenHsu over 5 years ago in reply to Dave Bell

Intellectual 980 points

Hi Dave,

Thank you for your reply, it is very helpful to us.

As you said, the Linux driver now directly controls CPSW2G.

So if we want to bring up CPSW9G and test QSGMII (4 port).

In TI's design plan, will there be 5 ports (4 port)CPSW9G QSGMII + (1 port)CPSW2G in the Linux environment (ifconfig),

or Linux can only choose one of CPSW9G or CPSW2G to use.

0 Dave Bell over 5 years ago in reply to AllenHsu

TI__Genius 14680 points

Allen,

There will be the CPSW9G ports available. But to clarify the CPSW9G will be managed by the Ethernet Firmware on the R5F core. In the Linux environment there will be one ethX port to communicate. See http://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/latest/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/J7_CPSW9g_virt_mac.html.

and specifically for the binding: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/Documentation/devicetree/bindings/net/ti,cpsw-virt-mac.txt?h=ti-linux-4.19.y

Best regards,

Dave

0 AllenHsu over 5 years ago in reply to Dave Bell

Intellectual 980 points

Hi Dave,

Thank you for correcting some of my wrong thoughts.
From the Linux environment, if we bring up the CPSW9G, we can use ifconfig to get only one port which belong to CPSW9G.

So if we bring up the CPSW9G, under the Linux environment, will there be the following situation?

$ifconfig

eth0 <= CPSW2G

eth1 <= CPSW9G

0 Dave Bell over 5 years ago in reply to AllenHsu

TI__Genius 14680 points

Allen,

The eth[x] enumeration will depend on the order discovered based on the listing in the device tree

Aside from the initial enumeration process, you can rename the interfaces as well using netdev rules and re-map which is eth0 (or another name). See https://www.shellhacks.com/change-network-interface-name-eth0-eth1-eth2/ as an example (or search renaming in udev and 70-persistent-net.rules for other references)

Best regards,

Dave

0 AllenHsu over 5 years ago in reply to Dave Bell

Intellectual 980 points

Hi Dave,

What I actually want to ask is not the exact number,
but whether there will be two network cards in our Linux environment.
One of these two network cards can send data to CPSW2G, and another one can send data to CPSW9G.

0 Dave Bell over 5 years ago in reply to AllenHsu

TI__Genius 14680 points

Allen,

Yes, there will be two... one for CPSW2G and one for CPSW9G.

Best regards,

Dave

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TDA4VM: Why Linux information on A72 is sent to MCU Domain