Other Parts Discussed in Thread: TMDSEVM572X, DRA718
I test the Gbps PHY KSZ9031RNX speed and the bandwidth limit is about 380Mbps.
RGMII V2.0 specification define the clock to data delay 1.8ns.
AM5708 sets the TX clock to data 1ns and KSZ9031RNX sets the RX clock to data default delay 1.2ns.
So I modified the KSZ9031RNX register to add other 0.8ns delay on TX clock and 0.6ns delay on RX clock but the bandwidth limit is still about 380Mbps.
Do I miss anything?
Thanks.