C5504 UART

Hi:

I am testing the UART on the VC5504 in the loopback  and non-fifo mode. I am writing a character at a time and trying to read it back. I monitor bits 6 (TEMT) and 5 (THRE) of the LSR register to ensure that the holding register is ready to accept new data before I write to it. I am able to write data. Also, I am reading bit 0 (DR) of the LSR register to see if data is ready. However, the DR bit is never changing state from 0 to 1 indicating that data has been received. I don't know why I am not receiving data. I am following the UART initialization procedure on page 18 of SPRUF05. It is listed below. Could you please help? I don't know wht I am missing. Thanks a lot.

Cheers,

Mushtaq

#include "uart_init.h"

void uart_config(void)
{
 int i, divisor;

 //Enable Clock to UART.
 PCGCR1 &= 0xfffb; //Set bit 2 to 0 to enable uart clock.

 //Set parallel port to mode 1, i.e. uart,i2s2,i2s3, and spi. (bits 14-12)
 EBSR |= 0x1000;

 //Reset uart. CAUTION: This resets uart, spi, i2s2, and i2s3.
 PSRCR = 0x0050; //Count of system clock cycles for which SW reset is asserted in the next instruction.
 PRCR  &= 0x0080;     // Reset peripheral group four -- uart, spi, i2s2, and i2s3 (bit 7). 
 for(i=0;i<50;i++){}; //Wait.
 
 *(ioport unsigned int *)URPECR = 0x1fff;  //  disable UART Mushtaq 011911 uart Reset uart Tx and Rx. 

 //Mushtaq 011911 uart This is for testing.
 *(ioport unsigned int *)URLCR = 0x03;  // 8-bit, no parity checks, 1 stop

//Mushtaq 011911 uart Changed for c5504.CLOCK_CYCLES_PER_UART_SAMPLE changed in sysdef.h
 divisor = (CLOCK_CYCLES_PER_UART_SAMPLE) / 16; //Mushtaq 011911 Data sheet formula is (CPU clock)/(Baud rate *16)
 //mytemp = divisor;

 *(ioport unsigned int *)URDLL = divisor & 0xFF; //lower byte of divisor.
 *(ioport unsigned int *)URDLM = (divisor >> 8) & 0xFF; //upper byte of divisor.
 
 *(ioport unsigned int *)URIER = 0x07;  //  enable all interrupts (line status, xmit, recv)
  
//Mushtaq 011911 uart Changed for c5504.
 *(ioport unsigned int *)URFCR = 0x01;  //  FIFO enabled
 *(ioport unsigned int *)URFCR = 0x00;  // FIFO disabled.

 //URLCR Line Control Register
 *(ioport unsigned int *)URLCR = 0x03;  // 8-bit, no parity checks, 1 stop

 //URMCR Modem Control Register
 *(ioport unsigned int *)URMCR = 0x0010;  // No flow, loopback mode, and RTS disabled

 i = *(ioport unsigned int *)URRBR; //Mushtaq 011911 uart Clear any preexisting characters.
 
}

Int16 uart_putchar(Uint8 data)
{
 *(ioport unsigned int *)URTHR = data;
 return 0;
}

Int16 uart_getchar(Uint8 *data)
{
 *data = *(ioport unsigned int *)URRBR;
 return 0;
}

//////////////////////////////////////////////////////////

void main(void)
{
 Uint8 rx[256];
 Uint8 tx[256];
 Int16 i, errors;
 
 for(i = 0; i < 256; i++)
  {
   tx[i] = i;
   rx[i] = 0;
  }
  
 uart_config();
 
 for(i = 0; i < 256; i++)
  {
   while((*(ioport unsigned int *)URLSR & 0x60) == 0);
   
   uart_putchar(tx[i]);
   
   while((*(ioport unsigned int *)URLSR & 0x01) == 0);
   
   uart_getchar(&rx[i]);
  }
  
 for(i = 0; i < 256; i++)
  {
   if (tx[i] != rx[i])
    {
     printf("Error at index %d\n", i);
     errors++;
    }
  }
   
}