Hi,
I have a custom C5515 board that I'm trying to get into a minimum power state. It is currently running at 8MHz from the 32kHz oscillator with PLL enabled with the UART active with the core IDLEing and I've shut down all clocks I'm not using. The core is powered at 1V05 and all IO is 1V8 - the power being consumed from these rails is 2.3mW (700uA at 3V3 into the switchers) including external 1V8 memory etc. However I've got another 6mW on the 3V3 rail disappearing somewhere. The USB part of the chip is powered but it should all be shutdown (I've followed the sequence in the C5515 DSP System User Guide 1.5.3.4.1) - I can't see any specification for the quiescent current for the USB module into USB_VDDOSC, USB_VDDA3P3 and USB_VDDPLL - the System User Guide suggests there might be a reasonable quiescent:
"Stopping clocks to a peripheral only affects active power consumption; it does not affect leakage power consumption. USB leakage power consumption can be reduced to zero by not powering the USB."
but gives no clue to what it might be. What should I expect as a quiescent when the USB is shut down?
Many thanks,
Dave