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C5502 WDTOUT pulse width

Chris Shaw, Melbourne
Prodigy 210 points

Hi,

on our custom board we have connected the WDTOUT signal to a host microprocessor for detection of DSP failure. However, as far as I can tell the output pulse can only be stretched to a maximum of 4 clock cycles. If this is driven from the fast peripherals clocks which is configured at 150MHz then the output signal will only pulse for ~260ns. Is there any way to make this pulse wider? I guess one option would be to slow the fast peripherals clock, but that's not ideal.

Any other suggestions or is there something I've missed?

Chris

  • 0
    TI__Genius 14965 points

    Hi,

     

    You can widen WDTOUT signal to set Timer CLK Register (CLK) CLKDIV register.

    Regards,

    Hyun

  • 0 in reply to Hyun Kim
    Prodigy 210 points

    I didn't think I could.

    From Timers reference guide section 5.2 - Timer Clock Speed Register (CLK):

    The timer clock speed register (CLK) can be read to identify the internal clock
    frequency divider ratio for the timer. On the C5501/5502 device, the ratio is 1/1,
    meaning the internal timer clock (if used) is equal to the fast peripherals clock
    (SYSCLK1). Therefore, the CLKDIV field of CLK is always read as 0 on the
    C5501/5502 device.

    Chris