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OMAP-L138 startup GPIO State

Carson Au
Prodigy 80 points
Other Parts Discussed in Thread: OMAP-L138

How do I configure the state of the GPIO's upon reset of the processor?

Thanks

EDIT: The reason I ask is that I have to define some GPIO states before nRESETOUT is brought up high. Is this possible?

  • 0
    TI__Guru 62975 points

    Carson,

    It is not possible to configure the GPIO before RESETOUT toggles high.  The RESETOUT signal is an indication of when the device completes its hardware reset.  Peripherals are not accessible by software during reset.

    -Tommy

  • 0 in reply to tlee
    Prodigy 80 points

    Thanks for your answer! What would be the state of the OMAP pins during reset then? Are they undefined? I am observing a high output on at least two pins during this reset period (i.e. before RESETOUT is high).

  • 0 in reply to Carson Au
    TI__Guru 62975 points

    Carson,

    Please refer to this post here: http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/68326/249138.aspx

    We can help out with additional unanswered questions.

    -Tommy

  • 0 in reply to tlee
    Prodigy 80 points

    Thank you.

    In the OMAP-L138 Datasheet, on the terminal functions tables I notice that

    "During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a

    pull-up, an external pull-up can be used."

    For the pin I am looking at, the SPI0_SCSn2.

    However, for this pin, I am not observing quite the exact behaviour. The pin is low DURING reset, yes. But between RESET being brought up high, and RESETOUT being brought up high, the pin is HIGH. After RESETOUT is brough high, the pin is driven low again. 

    Is this behaviour normal? I wouldn't think that it is a very safe design to drive OMAP pins high between reset and resetout. Surely, this can be changed?  

  • 0 in reply to Carson Au
    TI__Guru 62975 points

    Carson,

    Are you looking at a board with an MII PHY?  This signal is also mux'd with the MII interface so it could be the board components pulling it high.  For example, on Logic's EVM SOM the SPI0_SCSn2 (aka MII_RXD0) signal acts as an input relative to the MII PHY.  If the signal is toggling, it's likely the PHY output or the pull-up resistor that is driving the transitions.

    -Tommy