TCI6638K2K: DDR3 failure @ 1600MT/s, works fine @ 1333 MT/s

Dhiraj Kiran1

Part Number: TCI6638K2K

Hello TI team...

Background

¨ One of our designs uses TI’s SOC (TCI6638K2K).

¨ DDR3A interface of the SOC is equipped with four 16-bit TwinDie DDR3 devices (Datasheet attached in the previous email).

Single Rank design.
ECC is not used in the design.
DDR3B interface is not equipped in the design.

¨ The memory absolutely works fine at 1333 MT/s

Issue Definition (@ 1600 MT/s)

¨ We see corrupted data during the 1^st and 4^th beats of every read burst (Burst-8). Data for the remaining 6 beats is intact.

Training and Levelling are successful and do not throw up any errors.
Read/Write Memory tests also pass.

Our Observations and Conclusions

¨ 64-bit Data (pertaining to Beats-1,4) keeps getting modified on consecutive reads. The data read out during the remaining beats stays consistent to the written data.

¨ Majority of bytes in the 64 bit data (pertaining to Beats-1,4) keep showing up with the written values once in a while indicating that this is a read issue.

¨ R0DGSL (Rank-0 DQS Gating System Latency) is not getting properly resolved during the automatic DQS training.

When we set this parameter manually (‘value read in the failure mode’ – 1) , we are able to get the memory working consistently.

Queries

¨ What is the exact definition for DGSL ? How do we statically calculate this parameter based on the board routing delays ?

¨ Can we set this parameter manually ? If not, how do we ensure proper resolution every time during automatic DQS training ?

¨ Please indicate if T_RTW is an important parameter ? Currently, this value is set to 0x0.

Please provide more details on how we can calculate this value. The description in the data sheet is not very clear.

¨ Is there any relation between T_RTW and DGSL ?

¨ Any other suggestions to resolve this issue are most welcome.

DDR3_SDRAM_DATA_SHEET.pdf K2 DDR3 Register Calc v1p60_31_01_V1_DDR1600_CL11_CWL8_17MAY.xlsx

Fullscreen VALUES_XCEL_BASELINED_PGCR0_COM.txt Download

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: PLL Control Register (PLLCR)
C66xx_0: GEL Output: DDR3A_PLLCR:			0x0001C000 (Address: 0x02329018)
C66xx_0: GEL Output: 	FRQSEL[19:18]:			PLL Reference clock ranges from 335MHz to 533MHz (0)
C66xx_0: GEL Output: Note: PLL Reference Clock should be 1/4 of DDR data rate. (i.e. 400MHz -> 1600MTs)
C66xx_0: GEL Output: ********************************************************

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: DRAM Timing Parameters Register 0 (DTPR0)
C66xx_0: GEL Output: DDR3A_DTPR0:			0xA19DBB66 (Address: 0x02329048)
C66xx_0: GEL Output: 	tRFC[31:26]:			Activate to Activate command delay (same bank) is 40 cycles
C66xx_0: GEL Output: 	tRRD[25:22]:			Activate to Activate command delay (diff banks) is 6 cycles
C66xx_0: GEL Output: 	tRAS[21:16]:			Activate to Precharge command delay is 29 cycles
C66xx_0: GEL Output: 	tRCD[15:12]:			Activate to Read/Write (on activated row) command delay is 11 cycles
C66xx_0: GEL Output: 	tRP[11:8]:			Precharge command period is 11 cycles
C66xx_0: GEL Output: 	tWTR[7:4]:			Internal write to read command delay is 6 cycles
C66xx_0: GEL Output: 	tRTP[3:0]:			Internal read to precharge command delay is 6 cycles
C66xx_0: GEL Output: ********************************************************

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: DRAM Timing Parameters Register 1 (DTPR1)
C66xx_0: GEL Output: DDR3A_DTPR1:			0x32868400 (Address: 0x0232904C)
C66xx_0: GEL Output: 	tWLO[29:26]:			Write leveling output delay is 12 cycles
C66xx_0: GEL Output: 	tWLMRD[25:20]:			Min delay from write leveling mode to first DQS edge is 40 cycles
C66xx_0: GEL Output: 	tRFC[19:11]:			Refresh to Refresh command delay is 208 cycles
C66xx_0: GEL Output: 	tFAW[10:5]:			4-bank activate period is 32 cycles
C66xx_0: GEL Output: 	tMOD[4:2]:			Load mode update delay is 12 cycles (0)
C66xx_0: GEL Output: 	tMRD[1:0]:			Load mode cycle time is 0 cycles
C66xx_0: GEL Output: ********************************************************

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: DRAM Timing Parameters Register 2 (DTPR2)
C66xx_0: GEL Output: DDR3A_DTPR2:			0x5002D200 (Address: 0x02329050)
C66xx_0: GEL Output: 	tCCD[31]:			Read to read and write to write command delay is 4 cycles (0)
C66xx_0: GEL Output: 	tRTW[30]:			Read to write command delay is standard bus turn around delay +1 clock (1)
C66xx_0: GEL Output: 	tRTODT[29]:			Read to ODT delay is 0, may come immediately after read post-amble (0)
C66xx_0: GEL Output: 	tDLLK[28:19]:			DLL locking time is 512 cycles
C66xx_0: GEL Output: 	tCKE[28:19]:			CKE minimum pulse width (tCKESR) is 5 cycles
C66xx_0: GEL Output: 	tXP[14:10]:			Power down exit delay is 20 cycles
C66xx_0: GEL Output: 	tXS[9:0]:			Self refresh exit delay is 512 cycles
C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: Mode Register 0 (MR0)
C66xx_0: GEL Output: DDR3A_MR0:				0x00001C70 (Address: 0x02329054)
C66xx_0: GEL Output: 	PD[12]:				Fast power down exit (DLL on) (1)
C66xx_0: GEL Output: 	WR[11:9]:			Write Recovery is 12 cycles (6)
C66xx_0: GEL Output: 	CL[6:4,2]:			11 cycles (14)
C66xx_0: GEL Output: ********************************************************

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: Mode Register 1 (MR1)
C66xx_0: GEL Output: DDR3A_MR1:				0x00000006 (Address: 0x02329058)
C66xx_0: GEL Output: 	AL[4:3]:			AL Disabled (0)
C66xx_0: GEL Output: 	RTT[9,6,2]:			ODT is RZQ/4 on SDRAM (1)
C66xx_0: GEL Output: 	DIC[5,1]:			Output Drive is RZQ/7 on SDRAM (1)
C66xx_0: GEL Output: 	DE[0]:				DLL Enabled on SDRAM (0)
C66xx_0: GEL Output: ********************************************************

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: Mode Register 2 (MR2)
C66xx_0: GEL Output: DDR3A_MR2:				0x00000058 (Address: 0x0232905C)
C66xx_0: GEL Output: 	RTTWR[10:9]:			Dynamic ODT is Disabled (0)
C66xx_0: GEL Output: 	CWL[5:3]:			CAS Write Latency is 8 cycles (3)
C66xx_0: GEL Output: 	SRT[7]:				Normal Operating Temperature Range (0)
C66xx_0: GEL Output: 	ASR[6]:				Auto Self-Refresh Power Management Enabled (64)
C66xx_0: GEL Output: 	PASR[2:0]:			Partial Array Self-Refresh is set to Full Array (0)
C66xx_0: GEL Output: ********************************************************

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: Impedance Control Register 1 (Address/Command/Control signals) (ZQ0CR1)
C66xx_0: GEL Output: DDR3A_ZQ0CR1:			0x0001005B (Address: 0x02329184)
C66xx_0: GEL Output: 	ZPROG-ODT[7:4]:			On-Die Termination is set to N/A (5)
C66xx_0: GEL Output: 	ZPROG-ZO[3:0]:			Output Impedance is set to 40ohms (11)
C66xx_0: GEL Output: ********************************************************

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: Impedance Control Register 1 (Data Lanes 0-3) (ZQ1CR1)
C66xx_0: GEL Output: DDR3A_ZQ1CR1:			0x0001005B (Address: 0x02329194)
C66xx_0: GEL Output: 	ZPROG-ODT[7:4]:			On-Die Termination is set to 60ohms (5)
C66xx_0: GEL Output: 	ZPROG-ZO[3:0]:			Output Impedance is set to 40ohms (11)
C66xx_0: GEL Output: ********************************************************

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: Impedance Control Register 1 (Data Lanes 4-7) (ZQ2CR1)
C66xx_0: GEL Output: DDR3A_ZQ2CR1:			0x0001005B (Address: 0x023291A4)
C66xx_0: GEL Output: 	ZPROG-ODT[7:4]:			On-Die Termination is set to 60ohms (5)
C66xx_0: GEL Output: 	ZPROG-ZO[3:0]:			Output Impedance is set to 40ohms (11)
C66xx_0: GEL Output: ********************************************************

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: DDR3A_PGCR0:			0xA8003E3F (Address: 0x02329008)
C66xx_0: GEL Output: DDR3A_PGCR1:			0x0280C425 (Address: 0x0232900C)
C66xx_0: GEL Output: DDR3A_PGCR2:			0x00F07A12 (Address: 0x0232908C)
C66xx_0: GEL Output: DDR3A_PLLCR:			0x0001C000 (Address: 0x02329018)
C66xx_0: GEL Output: DDR3A_MR0:			0x00001C70 (Address: 0x02329054)
C66xx_0: GEL Output: DDR3A_MR1:			0x00000006 (Address: 0x02329058)
C66xx_0: GEL Output: DDR3A_MR2:			0x00000058 (Address: 0x0232905C)
C66xx_0: GEL Output: DDR3A_MR3**************************
C66xx_0: GEL Output: DDR3A_DTPR0:			0xA19DBB66 (Address: 0x02329048)
C66xx_0: GEL Output: DDR3A_DTPR1:			0x32868400 (Address: 0x0232904C)
C66xx_0: GEL Output: DDR3A_DTPR2:			0x5002D200 (Address: 0x02329050)
C66xx_0: GEL Output: DDR3A_PTR0:			0x42C21590 (Address: 0x0232901C)
C66xx_0: GEL Output: DDR3A_PTR1:			0xD05612C0 (Address: 0x02329020)
C66xx_0: GEL Output: DDR3A_PTR2:			0x00083DEF (Address: 0x02329024)
C66xx_0: GEL Output: DDR3A_PTR3:			0x0D861A80 (Address: 0x02329028)
C66xx_0: GEL Output: DDR3A_PTR4:			0x0C827100 (Address: 0x0232902C)
C66xx_0: GEL Output: DDR3A_DCR:			0x0000040B (Address: 0x02329044)
C66xx_0: GEL Output: DDR3A_DTCR:			0x710035C7 (Address: 0x02329068)
C66xx_0: GEL Output: DDR3A_ZQ0CR1:			0x0001005B (Address: 0x02329184)
C66xx_0: GEL Output: DDR3A_ZQ1CR1:			0x0001005B (Address: 0x02329194)
C66xx_0: GEL Output: DDR3A_ZQ2CR1:			0x0001005B (Address: 0x023291A4)
C66xx_0: GEL Output: DDR3A_ZQ3CR1**************************
C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: ****************************************************************************************************************
C66xx_0: GEL Output: ***************** DDR3A Leveling Errors *********************
C66xx_0: GEL Output:  PGSR0[27]:	WEERR has 	** No Error **
C66xx_0: GEL Output:  PGSR0[26]:	REERR has 	** No Error **
C66xx_0: GEL Output:  PGSR0[25]:	WDERR has 	** No Error **
C66xx_0: GEL Output:  PGSR0[24]:	RDERR has 	** No Error **
C66xx_0: GEL Output:  PGSR0[23]:	WLAERR has 	** No Error **
C66xx_0: GEL Output:  PGSR0[22]:	QSGERR has 	** No Error **
C66xx_0: GEL Output:  PGSR0[21]:	WLERR has 	** No Error **
C66xx_0: GEL Output:  PGSR0[20]:	ZCERR has 	** No Error **

C66xx_0: GEL Output:  PGSR0[11]:	WEDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[10]:	REDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[9]:		WDDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[8]:		RDDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[7]:		WLADONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[6]:		QSGDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[5]:		WLDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[4]:		DIDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[3]:		ZCDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[2]:		DCDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[1]:		PLDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[0]:		IDONE is 	** Set **

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: Leveling Errors by Byte Lane:

C66xx_0: GEL Output: Byte Lane 0:
C66xx_0: GEL Output: 	DX0GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX0GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX0GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX0GSR2[0]:   RDERR has 		** No Error **
C66xx_0: GEL Output: 	DX0GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX0GSR0[24]:   QSGERR on Rank0 has 	** No Error **
C66xx_0: GEL Output: 	DX0GSR0[6]:    WLERR has 		** No Error **
C66xx_0: GEL Output: Byte Lane 1:
C66xx_0: GEL Output: 	DX1GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX1GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX1GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX1GSR2[0]:   RDERR has 		** No Error **
C66xx_0: GEL Output: 	DX1GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX1GSR0[24]:   QSGERR on Rank0 has 	** No Error **
C66xx_0: GEL Output: 	DX1GSR0[6]:    WLERR has 		** No Error **
C66xx_0: GEL Output: Byte Lane 2:
C66xx_0: GEL Output: 	DX2GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX2GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX2GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX2GSR2[0]:   RDERR has 		** No Error **
C66xx_0: GEL Output: 	DX2GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX2GSR0[24]:   QSGERR on Rank0 has 	** No Error **
C66xx_0: GEL Output: 	DX2GSR0[6]:    WLERR has 		** No Error **
C66xx_0: GEL Output: Byte Lane 3:
C66xx_0: GEL Output: 	DX3GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX3GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX3GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX3GSR2[0]:   RDERR has 		** No Error **
C66xx_0: GEL Output: 	DX3GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX3GSR0[24]:   QSGERR on Rank0 has 	** No Error **
C66xx_0: GEL Output: 	DX3GSR0[6]:    WLERR has 		** No Error **
C66xx_0: GEL Output: Byte Lane 4:
C66xx_0: GEL Output: 	DX4GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX4GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX4GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX4GSR2[0]:   RDERR has 		** No Error **
C66xx_0: GEL Output: 	DX4GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX4GSR0[24]:   QSGERR on Rank0 has 	** No Error **
C66xx_0: GEL Output: 	DX4GSR0[6]:    WLERR has 		** No Error **
C66xx_0: GEL Output: Byte Lane 5:
C66xx_0: GEL Output: 	DX5GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX5GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX5GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX5GSR2[0]:   RDERR has 		** No Error **
C66xx_0: GEL Output: 	DX5GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX5GSR0[24]:   QSGERR on Rank0 has 	** No Error **
C66xx_0: GEL Output: 	DX5GSR0[6]:    WLERR has 		** No Error **
C66xx_0: GEL Output: Byte Lane 6:
C66xx_0: GEL Output: 	DX6GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX6GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX6GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX6GSR2[0]:   RDERR has 		** No Error **
C66xx_0: GEL Output: 	DX6GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX6GSR0[24]:   QSGERR on Rank0 has 	** No Error **
C66xx_0: GEL Output: 	DX6GSR0[6]:    WLERR has 		** No Error **
C66xx_0: GEL Output: Byte Lane 7:
C66xx_0: GEL Output: 	DX7GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX7GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX7GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX7GSR2[0]:   RDERR has 		** No Error **
C66xx_0: GEL Output: 	DX7GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX7GSR0[24]:   QSGERR on Rank0 has 	** No Error **
C66xx_0: GEL Output: 	DX7GSR0[6]:    WLERR has 		** No Error **
C66xx_0: GEL Output: Byte Lane 8:
C66xx_0: GEL Output: 	DX8GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX8GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX8GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX8GSR2[0]:   RDERR has 		** No Error **
C66xx_0: GEL Output: 	DX8GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX8GSR0[24]:   QSGERR on Rank0 has 	** No Error **
C66xx_0: GEL Output: 	DX8GSR0[6]:    WLERR has 		** No Error **
C66xx_0: GEL Output: ****************************************************************************************************************
C66xx_0: GEL Output: ****************************************************************************************************************
C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: DDR SDRAM Configuration Register (SDCFG)
C66xx_0: GEL Output: DDR3AEMIF_SDCFG:			0x6200CE62 (Address: 0x21010008)
C66xx_0: GEL Output: 	SDRAM Type[31:29]:   		DDR3 (3)
C66xx_0: GEL Output: 	SDRAM Drive[27:25]:  		RZQ/4 (1)
C66xx_0: GEL Output: 	Dynamic ODT[23:22]:  		OFF (0)
C66xx_0: GEL Output: 	CAS Write Latency[16:14]:	8 (3)
C66xx_0: GEL Output: 	Data Bus Width[13:12]: 		64-bit (0)
C66xx_0: GEL Output: 	CAS Latency[11:8]:		11 (14)
C66xx_0: GEL Output: 	Banks per SDRAM[6:5]: 		8 (3)
C66xx_0: GEL Output: 	Chip Select Setup[3]: 		DCE0# (0)
C66xx_0: GEL Output: 	Page Size[1:0]:    		1024 word page (2)
C66xx_0: GEL Output: ********************************************************

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: SDRAM Refresh Control Register (SDRFC)
C66xx_0: GEL Output: DDR3AEMIF_SDRFC:			0x00000C34 (Address: 0x21010010)
C66xx_0: GEL Output: 	INITREF_DIS[31]:		Normal operation
C66xx_0: GEL Output: 	REFRESH_RATE[15:0]:		3124 (REFRESH_RATE = Refresh period * DDR3 clock frequency.)
C66xx_0: GEL Output: ********************************************************

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: SDRAM Timing 1 Register (SDTIM1)
C66xx_0: GEL Output: DDR3AEMIF_SDTIM1:			0x166C9875 (Address: 0x21010018)
C66xx_0: GEL Output: 	T_WR[29:25]:			11 cycles (+1)
C66xx_0: GEL Output: 	T_RAS[24:18]:			27 cycles (+1)
C66xx_0: GEL Output: 	T_RC[17:10]:			38 cycles (+1)
C66xx_0: GEL Output: 	T_RRD[9:4]:			7 cycles (+1)
C66xx_0: GEL Output: 	T_WTR[3:0]:			5 cycles (+1)
C66xx_0: GEL Output: ********************************************************

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: SDRAM Timing 2 Register (SDTIM2)
C66xx_0: GEL Output: DDR3AEMIF_SDTIM2:			0x0000014A (Address: 0x2101001C)
C66xx_0: GEL Output: 	T_RTW[12:10]:			0 cycles (+1)
C66xx_0: GEL Output: 	T_RP[9:5]:			10 cycles (+1)
C66xx_0: GEL Output: 	T_RCD[4:0]:			10 cycles (+1)
C66xx_0: GEL Output: ********************************************************

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: SDRAM Timing 3 Register (SDTIM3)
C66xx_0: GEL Output: DDR3AEMIF_SDTIM3:			0x435DFF53 (Address: 0x21010020)
C66xx_0: GEL Output: 	T_XP[31:28]:			4 cycles (+1)
C66xx_0: GEL Output: 	T_XSNR[27:18]:			215 cycles (+1)
C66xx_0: GEL Output: 	T_XSRD[17:8]:			511 cycles (+1)
C66xx_0: GEL Output: 	T_RTP[7:4]:			5 cycles (+1)
C66xx_0: GEL Output: 	T_CKE[3:0]:			3 cycles (+1)
C66xx_0: GEL Output: ********************************************************

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: SDRAM Timing 4 Register (SDTIM4)
C66xx_0: GEL Output: 	DDR3AEMIF_SDTIM4:		0x543F0CFF (Address: 0x21010028)
C66xx_0: GEL Output: 	T_CSTA[31:28]:			4 cycles (+1)
C66xx_0: GEL Output: 	T_CKESR[27:24]:			3 cycles (+1)
C66xx_0: GEL Output: 	ZQ_ZQCS[23:16]:			93 cycles (+1)
C66xx_0: GEL Output: 	T_RFC[13:4]:			1013 cycles (+1)
C66xx_0: GEL Output: 	T_RAS_MAX[3:0]:(should be 0xF)	3 cycles
C66xx_0: GEL Output: ********************************************************

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: SDRAM Output Impedance Calibration Configuration Register (ZQCFG)
C66xx_0: GEL Output: 	DDR3AEMIF_ZQCFG:		0x70073200 (Address: 0x210100C8)
C66xx_0: GEL Output: 	ZQ_CS1EN[31]:			ZQ calibration for Rank 2 is Disabled (0)
C66xx_0: GEL Output: 	ZQ_CS0EN[31]:			ZQ calibration for Rank 1 is Enabled (1)
C66xx_0: GEL Output: 	ZQ_DUALCALEN[29]:		Dual ZQ calibration is Enabled (1)
C66xx_0: GEL Output: 	ZQ_SFEXITEN[28]:		ZQ calibration on self-refresh, Active power-down and precharge power-down exit is Enabled (1)
C66xx_0: GEL Output: 	ZQ_ZQCL_MULT[18:16]:		7 cycles
C66xx_0: GEL Output: 	ZQ_REFINTERVAL[15:0]:		Refresh periods between ZQCS commands is 12800 (+1)
C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: ****************************************************************************************************************

xtcievmk2x_arm_RAC_1600_DHIR_debug_17MAY.gel

over 5 years ago

0 Tom Johnson 16214 over 5 years ago

TI__Mastermind 46460 points

Dhiraj,

We do not have support for controlling the leveling through software. The support model that we have is hardware driven leveling. As you have already seen, this is working robustly at 1333MT/s. It appears that you are having problems with the DQS Gate System Latency adaptation. These problems are due to signal integrity deficiencies in your layout. These leveling functions operate independently for each byte lane. Are you seeing these problems on every byte lane or only on certain byte lanes? If so, which ones?

Tom

0 Dhiraj Kiran1 over 5 years ago in reply to Tom Johnson 16214

Prodigy 120 points

Hello Tom,

Thanks a lot for the quick response.

To answer your question, we are predominantly seeing issues with the upper 4 bytes lanes. Very rarely, we see the 0th byte lane having an issue. Every leveling iteration, we see different bytes having issues.

1] One additional observation : With the PHY side DQS/DQ ODT change from 60 Ohms to 40 Ohms, the DQS gating system seems to be able to resolve the latency successfully in most of the iterations (1 failure in 10 iterations). Please comment on this observation. Does this mean that the design is too marginal ?

2] Considering that 1600MT/s is very close to 1333MT/s...do you see any risk for the operation at 1333MT/s ?

The only aspect that I can thick of, is that the vias pertaining to DQ/DQS are not back drilled. Depending on the layers the various octets are routed, these can result in stubs at both the DDR3 end and the DSP end.

Should we backdrill the vias in the next revision of the design ? Please advice.

4] The signals look ok on the oscilloscope. The DQS to DQ relation (Edge aligned) on the read phase looks fine.

5] One addition point...The octets that fail the DQS Gate System's Latency adaptation, start working once the latency value is manually decremented by one from the automatically arrived at value. After the automated leveling is completed, I read the R0DGSL value, decrement it by 1 and program it into the same register. These octets start working.

Any other pointers to help us...

Thanks,

Dhiraj

0 Tom Johnson 16214 over 5 years ago in reply to Dhiraj Kiran1

TI__Mastermind 46460 points

Dhiraj,

1] We are predominantly seeing issues with the upper 4 bytes lanes. Very rarely, we see the 0th byte lane having an issue. Every leveling iteration, we see different bytes having issues. One additional observation : With the PHY side DQS/DQ ODT change from 60 Ohms to 40 Ohms, the DQS gating system seems to be able to resolve the latency successfully in most of the iterations (1 failure in 10 iterations). Please comment on this observation. Does this mean that the design is too marginal?

TI: This in indication of a signal integrity sensitivity. By changing this ODT value, you are changing the PHY-side termination. This will affect the energy reflected at this point.

2] Considering that 1600MT/s is very close to 1333MT/s...do you see any risk for the operation at 1333MT/s?

TI: Actually, I do not think of these rates as being close. 1333MT/s has lots of timing margin with this product family. The timing margin at 1600MT/s is very small. Our customers often have difficulty obtaining robust operation at the higher speed of 1600MT/s but 1333MT/s is easy to attain robust operation. Some have even decided to operate at an intermediate rate like 1500MT/s since they could not quite optimize their layout for robust operation at 1600MT/s.

3] The DQS/DQ routing is point to point, all 8 octets with their DQS are length matched to 54mm +/- 0.5mm. DQ lines are Impedance controlled to 50 Ohms (Single Ended). DQS_P/N are impedance controlled to 100Ohms (Differential). These are routed in Single stripline layers. Every octet with the associated DQS_P/N is routed in the same layer. There does not seem to be much scope for signal integrity issues. The only aspect that I can think of, is that the vias pertaining to DQ/DQS are not back drilled. Depending on the layers the various octets are routed, these can result in stubs at both the DDR3 end and the DSP end. Should we backdrill the vias in the next revision of the design ? Please advice.

TI: Back-drilling the vias can definitely help if the via stubs are long. Are the DQ and DQS routes close to the bottom of the board or close to the top? How thick is your board and which layers carry DDR Data group signals? Do you have all Data group signals within a single routing group on a single later with the same number of vias? Do all Data group routes have a solid Ground reference plane? What about trace spacing? What is the spacing between routes within a Data group? What is the spacing to traces in other groups?

4] The signals look ok on the oscilloscope. The DQS to DQ relation (Edge aligned) on the read phase looks fine.

TI: Leveling is primarily about CLK and DQS routing delays and signal integrity. DQ bit deskew can provide additional margin but this is optional (as long as proper Data group length matching is correct). Therefore, success or failure with leveling is primarily about the quality of the CLK and DQS signals. Please provide a scope capture of the DQS/DQS# during a Read burst with the probes attached very close to the processors PHY pins. Some layouts have benefited by having 15 ohm resistors added in series with the DQS/DQS# pins located close to the PHY.

TI: Understood. This shows that the marginality is related with the Read Gate Leveling. However, this is not a robust solution. I expect that this is providing marginal success. We need to get the hardware leveling to resolve to an optimum point.

TI: You mentioned that errors occur in the 1^st and 4^th beat of a burst. Can you provide data patterns showing this?

Tom

0 Dhiraj Kiran1 over 5 years ago in reply to Tom Johnson 16214

Prodigy 120 points

Thanks a lot, Tom for the elaborate pointers...

1] TI: Actually, I do not think of these rates as being close. 1333MT/s has lots of timing margin with this product family. The timing margin at 1600MT/s is very small. Our customers often have difficulty obtaining robust operation at the higher speed of 1600MT/s but 1333MT/s is easy to attain robust operation. Some have even decided to operate at an intermediate rate like 1500MT/s since they could not quite optimize their layout for robust operation at 1600MT/s.

Dhiraj : We need to get the design working at 1600MT/s. This is absolutely mandatory for us. We intend to tweak the design in our next revision to achieve this. Any suggestions to achieve this will be most welcome.

How do we achieve the intermediate rate of 1500MT/s ? Which PLL has to be retuned and what should be the PLL configuration parameters ?

2. TI: Back-drilling the vias can definitely help if the via stubs are long. Are the DQ and DQS routes close to the bottom of the board or close to the top? How thick is your board and which layers carry DDR Data group signals? Do you have all Data group signals within a single routing group on a single later with the same number of vias? Do all Data group routes have a solid Ground reference plane? What about trace spacing? What is the spacing between routes within a Data group? What is the spacing to traces in other groups?

Dhiraj :

a. 2.25mm is the board thickness, an 18 layer board

b. TI-DSP is on the top and the DDR3 devices (4 nos, 16bit TwinDie parts) are placed on the bottom side.

c. "DQ[7:0], DQS0_P/N <> Layer-12", "DQ[15:8], DQS1_P/N <> Layer-14", "DQ[23:16], DQS2_P/N <> Layer-14", "DQ[31:24], DQS3_P/N <> Layer-12", "DQ[39:32], DQS4_P/N <> Layer-14", "DQ[47:40], DQS5_P/N <> Layer-05", "DQ[55:48] <> Layer-07, DQS6_P/N <> Layer-5", "DQ[63:56] <> Layer-07, DQS7_P/N <> Layer-7"

The last two octets do not have the corresponding DQS routed in the same layers. Is this a cause for concern since the layers 5 and 7 are not too far apart ?

d. 4.5mils : Trace to Trace spacing within Data Group, 4.5mils : Trace to Trace spacing between two groups, 12mils : Spacing to unrelated traces.

Since all Data groups are length matched to 54mm+/-0.5mm, we did not have a larger spacing between two data groups.

e. All signal layers are single strip lines...Every signal layer is sandwiched between two solid reference ground planes.

3. TI: Leveling is primarily about CLK and DQS routing delays and signal integrity. DQ bit deskew can provide additional margin but this is optional (as long as proper Data group length matching is correct). Therefore, success or failure with leveling is primarily about the quality of the CLK and DQS signals. Please provide a scope capture of the DQS/DQS# during a Read burst with the probes attached very close to the processors PHY pins. Some layouts have benefited by having 15 ohm resistors added in series with the DQS/DQS# pins located close to the PHY.

Dhiraj : CLK_P/N is daisy chained to the 4 DDR3 devices. DQSn_P/N (8 nos) are point to point. All DQS_P/N are length matched to 54mm (+/-0.5mm).

a. "51.0mm <> CLK_P/N to DDR3-1"

b. "61.7mm <> CLK_P/N to DDR3-2"

c. "72.4mm <> CLK_P/N to DDR3-3"

d. "83.1mm <> CLK_P/N to DDR3-4"

Will share the scope captures today.

How do the 15 Ohms series resistors on DQS_P/N closer to the TI-DSP help ? Do these dampen the reflections ?

4. TI: You mentioned that errors occur in the 1st and 4th beat of a burst. Can you provide data patterns showing this

Dhiraj : [Using Code Composer Studio] I have prefilled the locations to 0. I have written 0x1234567812345678 into 0x80000000 and 55AA55AA55AA55AA into 0x80000028.

First Read :

0x80000000 1200000012345678 0000000000000000 0000000000000000 0000000000000000 00AA550000000000

0x80000028 55AA55AA55AA55AA 0000000000000000 0000000000000000 0000000000000000 0000000000000000

0x80000050 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000

0x80000078 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000

Second Read :

0x80000000 1200000012345678 0000000000000000 0000000000000000 0000000000000000 00AA558000000000

0x80000028 55AA55AA55AA55AA 0000000000000000 0000000000000000 0000000000000000 0000000000000000

0x80000050 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000

0x80000078 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000

Third Read :

0x80000000 1200006812345678 0000000000000000 0000000000000000 0000000000000000 00AA55A800000000

0x80000028 55AA55AA55AA55AA 0000000000000000 0000000000000000 0000000000000000 0000000000000000

0x80000050 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000

0x80000078 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000

Thanks,

Dhiraj

0 Dhiraj Kiran1 over 5 years ago in reply to Dhiraj Kiran1

Prodigy 120 points

Hello Tom,

Attaching the waveforms.

CLK_P/N and DQS7_P/N captured together...

Note : CLK_P/N waveform is inverted in the captures as the positive of the High speed Differential Probe was soldered to CLK_N and the negative of the probe was soldered to CLK_P. I apologize for the mistake.

1. 1333, 60Ohms ODT on the PHY side

2. 1600, 60Ohms ODT on the PHY side

3. 1600, 40Ohms ODT on the PHY side

A few additional queries...

a] It is possible to achieve 1600MT/s reliable operation by ensuring strict layout design. Please confirm.

b] There is no limitation on the DDR3 Controller/PHY side, that will prevent the 1600MT/s operation. Please confirm.

0 Tom Johnson 16214 over 5 years ago in reply to Dhiraj Kiran1

TI__Mastermind 46460 points

Dhiraj,

I had hoped to see the DQS and DQS# signals separately. However, in the differential view, we can still see the variations in the ring-back after the DQS signals are no longer driven. I am told that when the Read Gate Leveling fails like this, it is due to the size of the reflections on these signals at the end of the read burst. The PHY sees these as a valid, 5th DQS pulse and aligns the read gate with an offset. Can you compare this signal between a byte lane that never fails and one that often fails with both the 60 ohm and 40 ohm ODT settings? Additional question: what bit field are you changing to vary this 'PHY-side ODT' setting?

Tom

0 Tom Johnson 16214 over 5 years ago in reply to Tom Johnson 16214

TI__Mastermind 46460 points

Dhiraj,

a] It is possible to achieve 1600MT/s reliable operation by ensuring strict layout design. Please confirm.

TI: Absolutely. We have many customers shipping product with operation at 1600MT/s. The K2H EVM operates both DDR3 interfaces at 1600MT/s.

b] There is no limitation on the DDR3 Controller/PHY side, that will prevent the 1600MT/s operation. Please confirm.

TI: As stated above, there is no limit in the DDR3 Controller preventing operation at 1600MT/s.

Tom

0 Tom Johnson 16214 over 5 years ago in reply to Tom Johnson 16214

TI__Mastermind 46460 points

Dhiraj,

1] We need to get the design working at 1600MT/s. This is absolutely mandatory for us. We intend to tweak the design in our next revision to achieve this. Any suggestions to achieve this will be most welcome. How do we achieve the intermediate rate of 1500MT/s? Which PLL has to be retuned and what should be the PLL configuration parameters?

TI: The DDR3A PLL is fully programmable. You are already using this to configure for 1333MT/s and 1600MT/s. Please refer to section 11.6 in the Data Manual and also refer to the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide (SPRUGV2) for more information.

Dhiraj:

a. 2.25mm is the board thickness, an 18 layer board

TI: OK

b. TI-DSP is on the top and the DDR3 devices (4 nos, 16bit TwinDie parts) are placed on the bottom side.

TI: This is a concern. Since you have the SOC on top and the DDR on the bottom, you will have long via stubs regardless of whether you route the signals near the top or the bottom. This type of design may require back drilling from both the top and the bottom. We strongly recommend keeping the memory on the same side as the SOC and then routing the data group nets close to the bottom to minimize the via stub length.

The last two octets do not have the corresponding DQS routed in the same layers. Is this a cause for concern since the layers 5 and 7 are not too far apart?

TI: Since they are close, this should be fine. We recommend keeping all routes in a data group on the same layer.

d. 4.5mils : Trace to Trace spacing within Data Group, 4.5mils : Trace to Trace spacing between two groups, 12mils : Spacing to unrelated traces.

TI: This is not acceptable. Using ‘W’ as the trace width, we recommend a center-to-center trace spacing of 5W in section 6.3.1 of the DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1C). You may get good operation at 4W center-to-center trace spacing with short traces. The crosstalk is much too high in a 2W layout.

Since all Data groups are length matched to 54mm+/-0.5mm, we did not have a larger spacing between two data groups.

TI: DDR layouts require sufficient space. This is not a valid rationale for not meeting the routing rules. Note that length matching is within the routing group. We do not require Data groups to be length matched to each other.

e. All signal layers are single strip lines...Every signal layer is sandwiched between two solid reference ground planes.

TI: This is probably the only reason it is functioning as good as it is.

3. TI: Leveling is primarily about CLK and DQS routing delays and signal integrity. DQ bit deskew can provide additional margin but this is optional (as long as proper Data group length matching is correct). Therefore, success or failure with leveling is primarily about the quality of the CLK and DQS signals. Some layouts have benefited by having 15 ohm resistors added in series with the DQS/DQS# pins located close to the PHY.

Dhiraj : How do the 15 Ohms series resistors on DQS_P/N closer to the TI-DSP help? Do these dampen the reflections?

TI: They do dampen the reflections on the DQS/DQS# signals when the lines are not driven.

4. TI: You mentioned that errors occur in the 1st and 4th beat of a burst. Can you provide data patterns showing this

Dhiraj : [Using Code Composer Studio] I have prefilled the locations to 0. I have written 0x1234567812345678 into 0x80000000 and 55AA55AA55AA55AA into 0x80000028.

TI: CCS memory window displays can be deceiving. Block writes and reads from a processor core or EDMA provide a much clearer picture. I recommend that you write a unique pattern to a block of 512 bytes and then read it back as a block and compare for bad values. Repeated reads also return different results which is also informative. Since every read from DDR results in an 8-strobe read burst, you will have a clearer indication if this is a burst-boundary issue or a marginal read issue by reading in block mode.

Tom

0 Dhiraj Kiran1 over 5 years ago in reply to Tom Johnson 16214

Prodigy 120 points

Hello Tom,

1] TI : I had hoped to see the DQS and DQS# signals separately. However, in the differential view, we can still see the variations in the ring-back after the DQS signals are no longer driven. I am told that when the Read Gate Leveling fails like this, it is due to the size of the reflections on these signals at the end of the read burst. The PHY sees these as a valid, 5th DQS pulse and aligns the read gate with an offset.

Dhiraj : We have currently enabled Dynamic ODT on the PHY side. Keeping the ODT enabled all the time should help here. Please share your comments on this.

2] TI : Can you compare this signal between a byte lane that never fails and one that often fails with both the 60 ohm and 40 ohm ODT settings?

Dhiraj : I will do this tomorrow and share the waveforms.

3] TI : Additional question: what bit field are you changing to vary this 'PHY-side ODT' setting?

Dhiraj : The registers are DDR3A_ZQnCR1

Thanks,

Dhiraj

0 Dhiraj Kiran1 over 5 years ago in reply to Dhiraj Kiran1

Prodigy 120 points

TI : Additional question: what bit field are you changing to vary this 'PHY-side ODT' setting?

Dhiraj : The registers are DDR3A_ZQnCR1, bits [7:4]

1000 : 40 Ohms

0101 : 60 Ohms

Thanks,

Dhiraj

0 Tom Johnson 16214 over 5 years ago in reply to Dhiraj Kiran1

TI__Mastermind 46460 points

Dhiraj,

The PHY-side ODT is not the same as Dynamic ODT (DYN_ODT) as a setting in the SDRAM. We do not support DYN_ODT in this controller and it must not be enabled. Also note that the setting of 40 ohms for the DDR3A_ZQnCR1, bits [7:4], is not a characterized option. That is why the REG_CALC worksheet does not enable this setting.

Tom

0 Dhiraj Kiran1 over 5 years ago in reply to Tom Johnson 16214

Prodigy 120 points

Tom,

Thanks a lot for the clarification.

1] I probed the read DQSn_P/N for the working octets. I do not see much difference from the waveforms captured for the non-working octets.

2] Also, the waveforms do not change significantly for the 1333 MT/s case. Does this mean that the design is marginal for the lower data rate as well ?

3] For a DQS pair (P and N), is the input on the TI-DSP side, a differential mode receiver ? Or is the DQS_P used as a single ended signal to sample in 1, 3, 5 and 7 beats, while the DQS_N is used to sample in 2, 4, 6 and 8 beats of the burs ?

4] One other query...We see two registers on the TI-DSP side to control the DSP side ODT.

SDCFG and ZQnCR1

a. SDCFG[27:25] : Enable ODT and select termination resistor value

SDCFG[23:22] : Enable or Disable Dynamic ODT

b. ZQnCRN1[7:4] : ODT divide select

Please elaborate the significance of the two registers.

Best Regards,
Dhiraj

0 Tom Johnson 16214 over 5 years ago in reply to Dhiraj Kiran1

TI__Mastermind 46460 points

Dhiraj,

1] I probed the read DQSn_P/N for the working octets. I do not see much difference from the waveforms captured for the non-working octets.

TI: There was not a lot of difference between the 40 and 60 ohm PHY termination but you saw a difference in behavior. And yes, there was a difference seen between the 40 and 60 ohm images provided above.

2] Also, the waveforms do not change significantly for the 1333 MT/s case. Does this mean that the design is marginal for the lower data rate as well?

TI: Again, if you go back and look at the 1333MT/s and the 1600MT/s waveforms provided, there is a noticeable difference. Were you able to collect the single-ended DQS/DQS READ wavewforms?

3] For a DQS pair (P and N), is the input on the TI-DSP side, a differential mode receiver? Or is the DQS_P used as a single ended signal to sample in 1, 3, 5 and 7 beats, while the DQS_N is used to sample in 2, 4, 6 and 8 beats of the burst?

TI: The single-ended DSQ/DQS# signals do not latch even/odd edges of the burst like you describe. The results would look very different if that were the case.

4] One other query...We see two registers on the TI-DSP side to control the DSP side ODT.

SDCFG and ZQnCR1

a. SDCFG[27:25] : Enable ODT and select termination resistor value

SDCFG[23:22] : Enable or Disable Dynamic ODT

b. ZQnCRN1[7:4] : ODT divide select

Please elaborate the significance of the two registers.

TI: I referred to this previously. The PHY-side termination in ZQnCRN1[7:4] should not have been called ODT as this causes confusion. ODT is an optional SDRAM functionality controllable through the SDRAM’s Mode Registers which can be controlled by the ODT input to the SDRAM. If you refer to DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1C) Figures 14 – 16 in section 6.5, you can see how these apply:

ZO, for DATA and ACCC comes from the ZQnCRN1[3:0] bitfields, ZPROG_ZO.
PHY ODT, for DATA READs comes from the ZQnCRN1[7:4] bitfields, ZPROG_ODT.
DDR_TERM sets SDCFG[27:25] bitfield and the RTT bits in the MR1 register.
DYN_ODT is an optional feature in the SDRAM that we do not support. It is disabled in the SDCFG[23:22] bitfield and the RTTWR bit in MR2.
SDRAM_DRIVE is set by the DIC bits in MR1.

Tom

0 Dhiraj Kiran1 over 5 years ago in reply to Tom Johnson 16214

Prodigy 120 points

Hello Tom,

Thanks a lot for the support provided for the current case. The clarifications have been very pro-active, crystal clear and they absolutely addressed the issue at hand in every possible way.

We can close the issue for now. I will reopen the issue in case we need any further clarifications.

Thanks,

Dhiraj

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TCI6638K2K: DDR3 failure @ 1600MT/s, works fine @ 1333 MT/s