TDA4VM: [C71 cache] Meet issues in C71 L1/L2 Cache performance test

lei fu1

Part Number: TDA4VM

Hello There,

In order to make good decision on C71 L1/L2 cache size setting. I am working on C71 L1/L2 cache performance testing. And i have made a detailed description and attached code in the email which send to TI-FAE mIng-zhong@ti.com, Please help us figure it out! Thanks a lot!

Besides, COuld you please tell me how to enable the MSMC cache in CCS test. also I use CCSV9.2 testing the performance of L2 cache with setting L1cache size=0K; But it shows:

Thanks a lot!

Best Regards,

Samuel

over 5 years ago

0 Shyam Jagannathan over 5 years ago

TI__Genius 10365 points

Hi Samuel,

L1D cache cannot be turned OFF in C7x DSP, it will be always ON but you can change the sizes as 8KB, 16KB, 32KB.

For turning ON L3 cache let me check with an expert and get back to you.

Regards,
Shyam

0 lei fu1 over 5 years ago in reply to Shyam Jagannathan

Expert 1640 points

Hi Shyam,

Thanks a lot for the L1 cache clarify. So my understand is L1D always have 8k cache. And L1D SRAM can be set 16KB~40KB; How about LUT. LUT buffer is exclude from L1D?

Best Regards,

Samuel

0 Shyam Jagannathan over 5 years ago in reply to lei fu1

TI__Genius 10365 points

Hi Samuel,

Please refer to section 6.5.3.3.2 C71x DSP L1 Data Memory in the TRM.

http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf

LUT is implemented in L1D so whatever SRAM size is available that can be given to LUT.

Regards,
Shyam

0 lei fu1 over 5 years ago in reply to Shyam Jagannathan

Expert 1640 points

Hi Shyam，

Thanks for your reply. this document is great. It's possible for you to provide the C71 cache performance result for us?

Best Regards,

SAMUEL

0 Karthik Ramanan over 5 years ago in reply to lei fu1

TI__Guru** 113810 points

Hi Shyam,

Is the C7x cache performance captured as part of the tests that we record in the datasheet?

Regards

Karthik

0 Shyam Jagannathan over 5 years ago in reply to Karthik Ramanan

TI__Genius 10365 points

Samuel,

Cache performance is applicable to a use-case or an algorithm in question. Different algorithm will have different data access patterns so we don't have a generic cache performance document. This is something we expect customers to benchmark their algorithm on our device by enabling caches.

Regards,
Shyam

0 lei fu1 over 5 years ago in reply to Shyam Jagannathan

Expert 1640 points

Hi Shyam,

Thanks for the reply, I already wrote an example, could you please contact TI-FAE Zhong Ming for the details.

PS: I have edited this post to remove the email address. It is not encouraged to share this information on the forum.

Best Regards,

Samuel

Processors

Processors forum

TDA4VM: [C71 cache] Meet issues in C71 L1/L2 Cache performance test