Creating a flash bootable hext file using ccsv4 and hex6x

Sean,

Unfortunately I am not the best person to talk about the device bootloader, but check below some references that can help you in creating the boot code. You can also get additional insights from a device perspective in the C6700 device forum.

Sean Bedford said:

So if I am right doing it this way CCS should put all the sections in the write memory spaces within the out file then the hex file is compiled with any sections that need to be loaded into the flash.  I am a bit unsure on which sections actually need to go in to the flash for the program to initialise.  I tried different setups but maybe someone could confirm the sections that need to go to the flash for me?

To address that I strongly suggest you checking two references:
- Look at chapter 14 of the C6000 Integration workshop in the Archived Workshops section of the page below:
http://processors.wiki.ti.com/index.php/Hands-On_Training_for_TI_Embedded_Processors

- Check the application note below. Although designed for C2000, it contains several tips and details about memory sections to be written to non-volatile memory.
http://www.ti.com/lit/pdf/spra958

Sean Bedford said:

2. The other method I have tried is using hex6x to specify the boot table then using the following boot code so that it reads the table from 0x90000400.

I strongly suggest checking the first reference I sent above; it uses hex6x to create the flash image file.

Sean Bedford said:

It also went in strange loops that didn’t match up with the symbols when I tired it in other configurations.  If anybody can offer any clarity on the best way to create a bootable .hex file from ccsv4 and help me along my way I would be very grateful.

The loops may be due to the device resetting itself or the bootloader in ROM keep trying different sources of valid boot code.

Hope this helps,
Rafael 

Hi,

 

Thank you for you input Rafael, it helped to give me a better idea of the best process.

 

Here is what I think I should be doing and am trying to make work.

1. Creating a 0x400 byte boot section in memory at the start of the IRAM and FLASH.
2. Putting assembler code in the boot sections (load from flash and run from IRAM) using a linker file and the boot code below.
3. Setting up the suggested run and load memory location in the rest of flash and IRAM (as per Table 2 in SPRA999A1).  I am doing this in the BIOS.
4. Building the .out file.
5. Using hex6x to convert the file to intel hex format with the following command arguments:

C:\CCS_projects\14du\Release\14du.out        /* input COFF file */

-i

-image

-zero

-memwidth 8

-map imu.map

-o imu.hex

 

ROMS

{

    FLASH: org = 0x90000000, len = 0x0040000, romwidth = 8, files = {imu.hex}

}

1. Loading the hex file to the flash with my custom flash loader program.

 

There are currently two visible issues with the process.  The obvious one that brought me here, it does not boot the program correctly.  I can see when I load CCS that the data is being copied from the flash to the IRAM.  When I try to connect to the DSP in CCS and load the symbols the code gets stuck in silly loops such as this section of my boot loader:

            mvkl  EMIF_CE2,A4      

      ||    mvkl  EMIF_CE2_V,B4

            mvkh  EMIF_CE2,A4

      ||    mvkh  EMIF_CE2_V,B4

            stw   B4,*A4

      ||    mvkl  EMIF_CE3,A4   

      ||    mvkl  EMIF_CE3_V,B4     ;

            mvkh  EMIF_CE3,A4

      ||    mvkh  EMIF_CE3_V,B4

            stw   B4,*A4

      ||    mvkl  EMIF_SDRAMCTL,A4     

      ||    mvkl  EMIF_SDRAMCTL_V,B4    ;

            mvkh  EMIF_SDRAMCTL,A4

I can skip past this by altering the PC and it gets stuck in another silly loop past that one the PC loops back to the above code.

 

The second issue which I am not sure of the effect of (could it be causing the first??) is that when translatting the .out file with hex6x I get the following warning:

>> WARNING: section ‘.XXX’ at 0XXXh falls in unconfigured memory <skipped>

 

The first lot of X’s corespond to the sections args, sts, trace and log and the second to addresses.  Im not really sure what any of these do. 

 

I thought args what something that was Initilized so why is the linker giving it a separate load address? I now trace, log and sts are something to do with the bios but cant see where to apply separate load and run addresses just a singley memory section can these be loaded into the flash to remove these warnings or do they require to be written to?

 

Again thank you for any help I am desprettly running out of ideas.

 

Sean

 

Here is the boat loader code that I am using:

    .ref    _c_int00

       

FLASH_START   .equ    0x90000400        ;flash start address

CODE_START    .equ    0x00000400        ;start of non boot code

CODE_SIZE     .equ    0x0003fc00        ;application code size in byte

 

;EMIF Register Addresses

EMIF_GCTL       .equ  0x01800000  ;EMIF global control

EMIF_CE1        .equ  0x01800004  ;address of EMIF CE1 control reg.

EMIF_CE0        .equ  0x01800008  ;EMIF CE0control

EMIF_CE2        .equ  0x01800010  ;EMIF CE2control

EMIF_CE3        .equ  0x01800014  ;EMIF CE3control

EMIF_SDRAMCTL   .equ  0x01800018  ;EMIF SDRAM control

EMIF_SDRAMTIM   .equ  0x0180001c  ;EMIF SDRAM timer

EMIF_SDRAMEXT   .equ  0x01800020  ;EMIF SDRAM extension

 

; EMIF Register Values for 6713 DSK

EMIF_GCTL_V     .equ  0x00000078  ;

EMIF_CE0_V      .equ  0xffffbf93  ;EMIF CE0 SDRAM -

;EMIF_CE1_V      .equ  0x02208802  ;EMIF CE1 Flash 8-bit

EMIF_CE1_V      .equ  0xffffff03  ;EMIF CE1 Flash 8-bit - timings default

EMIF_CE2_V      .equ  0x22a28a22  ;EMIF CE2 Daughtercard 32-bit async

EMIF_CE3_V      .equ  0x22a28a22  ;EMIF CE3 Daughtercard 32-bit async

;EMIF_SDRAMCTL_V .equ  0x47115000  ;EMIF SDRAM control

;EMIF_SDRAMTIM_V .equ  0x00000578  ;SDRAM timing (refresh)

;EMIF_SDRAMEXT_V .equ  0x000a8529  ;SDRAM extended control

EMIF_SDRAMCTL_V .equ  0x5748f000  ;EMIF SDRAM control - Rows ect setup right timings default

EMIF_SDRAMTIM_V .equ  0x005DC5DC  ;SDRAM timing (refresh) - timings default

EMIF_SDRAMEXT_V .equ  0x000a8529  ;SDRAM extended control - All timings

 

       .sect ".bootload"

      

;************************************************************************

;* CONFIGURE EMIF

;************************************************************************

        ;****************************************************************

        ; *EMIF_GCTL = EMIF_GCTL_V;

        ;****************************************************************

            mvkl  EMIF_GCTL,A4   

      ||    mvkl  EMIF_GCTL_V,B4

            mvkh  EMIF_GCTL,A4

      ||    mvkh  EMIF_GCTL_V,B4

            stw   B4,*A4

        ;****************************************************************

        ; *EMIF_CE0 = EMIF_CE0_V

        ;****************************************************************

            mvkl  EMIF_CE0,A4      

      ||    mvkl  EMIF_CE0_V,B4    

            mvkh  EMIF_CE0,A4

      ||    mvkh  EMIF_CE0_V,B4

            stw   B4,*A4

        ;****************************************************************

        ; *EMIF_CE1 = EMIF_CE1_V (setup for 8-bit async)

        ;****************************************************************

            mvkl  EMIF_CE1,A4      

      ||    mvkl  EMIF_CE1_V,B4

            mvkh  EMIF_CE1,A4

      ||    mvkh  EMIF_CE1_V,B4

            stw   B4,*A4

        ;****************************************************************

        ; *EMIF_CE2 = EMIF_CE2_V (setup for 32-bit async)

        ;****************************************************************

            mvkl  EMIF_CE2,A4      

      ||    mvkl  EMIF_CE2_V,B4

            mvkh  EMIF_CE2,A4

      ||    mvkh  EMIF_CE2_V,B4

            stw   B4,*A4

        ;****************************************************************

        ; *EMIF_CE3 = EMIF_CE3_V (setup for 32-bit async)

        ;****************************************************************

      ||    mvkl  EMIF_CE3,A4   

      ||    mvkl  EMIF_CE3_V,B4     ;

            mvkh  EMIF_CE3,A4

      ||    mvkh  EMIF_CE3_V,B4

            stw   B4,*A4

        ;****************************************************************

        ; *EMIF_SDRAMCTL = EMIF_SDRAMCTL_V

        ;****************************************************************

      ||    mvkl  EMIF_SDRAMCTL,A4     

      ||    mvkl  EMIF_SDRAMCTL_V,B4    ;

            mvkh  EMIF_SDRAMCTL,A4

      ||    mvkh  EMIF_SDRAMCTL_V,B4

            stw   B4,*A4

        ;****************************************************************

        ; *EMIF_SDRAMTIM = EMIF_SDRAMTIM_V

        ;****************************************************************

      ||    mvkl  EMIF_SDRAMTIM,A4     

      ||    mvkl  EMIF_SDRAMTIM_V,B4    ;

            mvkh  EMIF_SDRAMTIM,A4

      ||    mvkh  EMIF_SDRAMTIM_V,B4

            stw   B4,*A4

        ;****************************************************************

        ; *EMIF_SDRAMEXT = EMIF_SDRAMEXT_V

        ;****************************************************************

      ||    mvkl  EMIF_SDRAMEXT,A4     

      ||    mvkl  EMIF_SDRAMEXT_V,B4    ;

            mvkh  EMIF_SDRAMEXT,A4

      ||    mvkh  EMIF_SDRAMEXT_V,B4

            stw   B4,*A4  

;****************************************************************************

; copy sections

;****************************************************************************

 

_boot_start:

    mvkl  FLASH_START,B4 ;flash start address ->B4

    mvkh  FLASH_START,B4  

     

       mvkl  CODE_START,A4 ;apps code start address ->A4

       mvkh  CODE_START,A4

       zero  A1

      

_boot_loop1:

       ldb   *B4++,B5       ; flash read

       mvkl  CODE_SIZE-4,B6 ; B6 = BOOT_SIZE -1024

      

       add   1,A1,A1          ;A1+=1,inc outer counter

       ||    mvkh  CODE_SIZE-4,B6

      

       cmplt  A1,B6,B0

       nop   

       stb   B5,*A4++

       [B0]  b     _boot_loop1

       nop   5

 

;****************************************************************************

; jump to entry point

;****************************************************************************

      

       mvkl .S2 _c_int00, B0

       mvkh .S2 _c_int00, B0

       B    .S2 B0

       nop   5      

I have just noticed (typically last thing on a Friday) what I think is the main problem.  These are the first two lines on my .hex file:

:200000002A0002026A0048022800020268000002C0088000A63690022BFE7D030000000009

:2000200041298400EA010003FAD80400000000003636900292FEFF2F008000002A504C000C

 

The C6713 boot process is copying two bytes into each 32 bit space.  So the first hex line puts 2A in address 0x0 then 00 in address 0x4 and so on with 02, 02, 6A, 00, 48, 02, 28, 00, 02 ect.  This means it puts 28 in address space 0x20.  Which is where the next line starts it writing so over writes ¾ of the last line.

 

Now I don’t now what the assembly code should look like in memory so it is hard for me to say which part of the process is at fault.  Maybe someone here can help me narrow it down?  This is what the disassembly says to try and make what I have typed clearer.

 

            boot_start, $../boot.asm:18:45$:

0x00000000:   0000002A            MVK.S2        0x0000,B0

0x00000004:   00000000            NOP

0x00000008:   00000002            NOP

0x0000000C:   00000002            NOP

0x00000010:   0000006A            MVKH.S2       0x0000,B0

            boot_loop1:

0x00000014:   00000000            NOP

0x00000018:   00000048            EXT.S1        A0,0,0,A0

0x0000001C:   00000002            NOP

0x00000020:   00000041            .word         0x00000041

0x00000024:   00000029 ||         MVK.S1        0x0000,A0

0x00000028:   00000084 ||         LDHU.D2T1     *-B0[0],A0

0x0000002C:   00000000            NOP

0x00000030:   000000EA            MVKH.S2       0x10000,B0

 

My guess would be that either the boot loader thinks it is reading 32 bits of data per address space or I some how need to tell CCS to pad out the commands with 000000.

 

Any light that can be shed on this would be very much appreciated.

 

Sean

Solved it undencase anybody else is having problems.  There was a problem in the flash burning code caused by a pointer to a uint8_t array causing the extra 0's to be written into the flash.  After this was fixed it works without speifying all the seperate load and run addresses.  Just put all sections into the IRAM in the BIOS and make the boot code copy the contents of Flash directly over to IRAM before calling c_int00.

 

Sean