DDR PHY Control Register Read Latency (RL) Value

Charles Gervasi

According to the TMS320C674x Memory Controller Guide: Read Latency = CAS latency + round-trip board delay- 1. (Units are clock cycles.)

The minimum clock cycle period supported (150MHz) is 6.7ns. If propagation delay is 180ps/in, the traces would need to be 18 inches long to result in one clock cycle delay. What value should I use for round-trip board delay if my traces are just under one inch long?

Also is CAS latency a specification of the memory chips. For example, my memory chip's CAS#-to-CAS# delay t[CCD] is 2 clock cycles. Is that the same thing as CAS latency?

over 14 years ago

0 tlee over 14 years ago

TI__Guru 62975 points

Charles,

I recommend using RL = CAS Latency + 1. If the interface has timing issues, you can increase or decrease the number as necessary.

CAS latency and CAS#-to-CAS# are not the same. You should be able to find "CAS Latency" or "CL" in the DDR datasheet as in the attached example.

-Tommy

0 Charles Gervasi over 14 years ago in reply to tlee

Expert 2270 points

Tommy,

Thank you very much.

Your suggestion of RL = CAS Latency + 1 results in a greater value than the user guide's recommendation. It that because it's okay for this value to be too large but not too small, so a larger number gives you some headroom for unexpected tolerances?

Thanks,

0 tlee over 14 years ago in reply to Charles Gervasi

TI__Guru 62975 points

Charles,

Yes, the +1 gives the memory interface more slack time so the DDR will still function ok. I'm sure that RL = CL will also work for you, but I'd rather err on the side of caution at first and then speed things up later.

-Tommy

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DDR PHY Control Register Read Latency (RL) Value