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TDA4VM: RGMII TskewT

YUTAI LI1
Intellectual 400 points

Part Number: TDA4VM

Hi TI support team

RGMII timing

1. TXC have internal skew with TDL, I know skew have positive data 0.5ns and negative 0.5ns but I want to know which is clk delay(later) to data and which is clk early than data. 

    e,g, The negative 0.5ns  (-0.5ns) means clk delay (later) than data ?  The clk rise edge at right side to data signal.  Is it correct ?

           The positive 0.5ns (0.5ns) means clk early than data ? The clk rise edge at left side to data signal. Is it correct ?

   

         

2. The TXC have internal delay is always enable from datasheet.  is it correct ?

3. Where can i find the TXC / RXC internal delay value from datasheet. 

4. Why we can't disable the internal delay from TDA4 because most PHY support internal delay RGMII both TXC and RXC. 

Thanks

Yutai

  • 0
    TI__Guru 57037 points

    Yutai,

    We're looking into this.  It looks like the spec is suggesting edge aligned ... but you're right that we only support internal delay enabled mode so the clk/data should be offset by 1/4 cycle.  

    Regards,
    Kyle

  • 0 in reply to kcastille
    TI__Genius 17176 points

    The RGMII Switching Characteristics table in the datasheet is incorrect.  It is being updated to match the below table.

    Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
    No.       10Mbps     100Mbps     1000Mbps   Unit
          Min Typ Max Min Typ Max Min Typ Max  
    RGMII5 tosu(TD-TXC) Output setup time, RGMII[x]_TD[3:0] valid to
    RGMII[x]_TXC high/low    		 1.2     1.2     1.05(1)     ns
    tosu(TX_CTL-TXC) Output setup time, RGMII[x]_TX_CTL valid to
    RGMII[x]_TXC high/low    		 1.2     1.2     1.05(1)     ns
    RGMII6 toh(TD-TXC) Output hold time, RGMII[x]_TD[3:0] valid after
    RGMII[x]_TXC high/low    		 1.2     1.2     1.05(1)     ns
    toh(TX_CTL-TXC) Output hold time, RGMII[x]_TX_CTL valid after
    RGMII[x]_TXC high/low    		 1.2     1.2     1.05(1)     ns
    (1) 1000Mbps operation requires that the 4 data pins (RGMII[x]_TD[3:0]) and RGMII[x]_TX_CTL have their board propagation delays matched to within 50 ps of RGMII[x]_TXC.