Part Number: TDA2P-ACD
I have some issues with the boundary scan test of the TDA2PHVRQACDQ1.
Some DDR pins fails. I can not control and drive some level on this pins.
Some other pins I can not control also.
I can not control the described boundary scan pins. But the most importent pins are:
QSPI CLK pin R1 and R2
DDR2_WEN
DDR1_WEN
DDR2_CSN0
DDR1_CSN0
All these pins I can not drive by an level via boundary scan. If I run an boundary scan access to the QSPI I need control the CLK signal. Also for an boundary scan interconnection to the DDR RAM. I need to control the CS and WE singals.
For the QSPI I can control the CS, DQ0-DQ3 via boundary scan. But not for CLK.
The boundary scan cell description for CLK and CA and DQ0-DQ3 are the same structure. I think it is ok, but I can not verify an problem of the BSDL model. All these pins are defined as bidirectional!
I think a configuration is nesseccary to control these pins as decribe in the BSDL model. Or a wrong BSDL model are the probelm?
We hope you can help us to clarify the probem of the boundary scan function of these pins.
Best regards
Jan
