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TMS320C6657: PCIe hardware error injection

Daisuke Maeda
Guru 20205 points
Part Number: TMS320C6657

Our customer wants to use a hardware error injection for PCIe between C6657 and other devices. Because their system under development must comply with IEC 61784-3, the system needs to implement the fault injection test function for PCIe that is related field communication.

What hardware  error injection feature does the C6657 support for PCIe?

For example, the following features can be found in the PCIe User Guide.

 - INV_ECRC and INV_LCRC in DIAG_CTRL register
 - ACK_DISABLE in LANE_SKEW register

Is there any information for PCIe error injection?

Best regards,

Daisuke

  • 0
    TI__Mastermind 46460 points

    Daisuke,

    This will require some research.  We will get back to you soon.

    Tom

  • 0 in reply to Tom Johnson 16214
    Guru 20205 points

    Hi Tom-san,

    Thank you for your reply.

    I will ask our customer for more details for the error injection. If there are more details, I will post them.

    Best regards,

    Daisuke

  • 0 in reply to Tom Johnson 16214
    Guru 20205 points

    Hi Tom-san,

    Our customer refers to "Communication errors" section that specifies possible communication errors in IEC 61784-3:2016+AMD1:2017 CSV. In that section, specify the following eight types of communication errors.

     1) Corruption
     2) Unintended repetition
     3) Incorrect sequence
     4) Loss
     5) Unacceptable delay
     6) Insertion
     7) Masquerade
     8) Addressing

    The customer wants to test each communication error specified above for PCIe. For example, errors that should be injected between C6657 and other devices is as follows:

     - Send packets with random numbers instead of sequence numbers
     - Send a packet with an invalid 8B10B code
     - Delay or not send a completion packet

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Guru* 95265 points

    Daisuke-san,

    There is no internal PCIe error injection capability for the C6657 PCIE IP.  

    1) Corruption – could be caused by momentary disabling of the Tx output

    2) Unintended repetition – Not possible

    3) Incorrect sequence – Not possible

    4) Loss - could be caused disabling the Tx output

    5) Unacceptable delay – not possible

    6) Insertion – not possible

    7) Masquerade – not possible

    8) Addressing – not possible

    Normally error injection is done on the serial packets before they reach the device. That is for the errors they want to test, they need to inject the error in the PCIe packets on the wire. Here is a link to Error injector product that allow PCIe error injection. Please consider using an external hardware for such purpose:

    https://www.keysight.com/us/en/assets/7018-01996/brochures/5990-3222.pdf

    Regards, Eric

  • 0 in reply to lding
    Guru 20205 points

    Hi Eric-san,

    Thank you for your reply.

    The error injector supports PCI Express card form factor but does not support a chip-to-chip interconnect on-board or a board-to-board interconnect via a custom connector.

    Normally, is a prototype board or a bridge board that can be connected to the error injector used?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Guru* 95265 points

    Hi,

    The C6657 EVM can be converted to PCIEx4 connector via http://www.ti.com/tool/TMDXEVMPCI, this is an AMC to PCIE adapter. For the error injection card, it is PCIEx16. I am not sure if there any cables to connect them together. We typically buy such connectors from https://www.samtec.com/. They have a lots of different types, please check with them.

    Regards, Eric