Is PAGESIZE Setting Only a Function of # of Column Address Bits?

I would like to verify that the PAGESIZE setting is simply the number of address available on the memory chip's columns. This is from the memory controller guide:

My DDR2 chip is 32M x 16 bits.  It has 10 column bits:

So it as simple as selecting a page size of 1024 words (PAGESIZE=2) simply because there are 10 column bits?

Thanks,

CJ