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OSPI maximum clock frequency configuration

yajuan ma
Prodigy 220 points
Other Parts Discussed in Thread: DRA829

Hello everyone，

In order to increase the speed of OSPI FLASH data transmission, I need to adjust the clock provided to the flash to the maximum. At present, the flash I use is 1.8V, and the maximum SDR clock frequency is 200MHz. From the chip manual of DAR829, I know that DRA829 can provide 1.8V, and the maximum clock frequency of SDR is 133MHz. Does 133MHz here refer to the clock to the flash port after frequency division, or before the frequency division?
TI's demo program main_ospi_flash_test.c sets the OSPI clock to 133M in the INAC mode, but in OSPI_V0.c the open flash divides the clock by 32, so the divided clock is 4.2MHz, this value will be The clock frequency of the DRA829 is actually output to the flash port. I changed the frequency division factor to 4 and the flash will fail to open when the clock is 33.3MHz. I want to know what is the maximum frequency of DRA829 after crossover here?

Thank you!

  • 0
    TI__Expert 4015 points

    All of the data provided in the datasheet table labeled "OSPI switching characteristics" refers to max speed (min cycle time) of the OSPI bus.

    That said, where do you derive a maximum frequency of 133MHz SDR?  The datasheet table 5-106 gives the minimum cycle time of 6.02ns for SDR mode at 1.8V, if you use data training.  Without data training, the minimum cycle time is 7ns.

  • 0 in reply to z
    Prodigy 220 points

    Hi,Zack

        Thank you for your answer, but I still have the following questions:
    1. How to use data training to derive a maximum frequency of 133MHz SDR?
    2.TI's demo program main_ospi_flash_test.c sets the OSPI clock to 133MHz in the INDAC mode, but then divides the clock with a baud rate divider, so that I ended up on the clk pin of OSPI FLASH The actual clock frequency measured is the frequency after frequency division. So how should I make the clock frequency on the clk pin of OSPI FLASH be 133MHz?
    Thank you.

  • 0 in reply to yajuan ma
    TI__Expert 4015 points

    PHY training is done in the processor SDK, but only in DAC access mode.  In INDAC mode, the PHY is not enabled, and the baud divider is set to 32.