dm365 PLL2 configuration.

Andrew,

What PLL is the DDR getting its clock source from? You can check this by reading the PERI_CLKCTL register bit 27, if it’s the same as the ARM (which seems that you are programming and you don’t adjust the DDR timings as you modify frequencies, there is a big chance for weird behavior.  Additionally make sure that you are only using the documented mult/div ranges for the PLL values, as described in the ARM Subsystem guide http://focus.ti.com/lit/ug/sprufg5a/sprufg5a.pdf section 6.

regards,

miguel

Hello.

ARM core feeds by  PLLC2SYSCLK2.

DDR feeds by PLLC1SYSCLK7.

No one of next are forbidden, but no one of next works:

144000 (kHz), mul=3, div=0
180000 (kHz), mul=15, div=3
136000 (kHz), mul=17, div=5
126000 (kHz), mul=21, div=7
157714 (kHz), mul=23, div=6
171428 (kHz), mul=25, div=6
133333 (kHz), mul=25, div=8
178285 (kHz), mul=26, div=6
162000 (kHz), mul=27, div=7
174000 (kHz), mul=29, div=7
165333 (kHz), mul=31, div=8
158400 (kHz), mul=33, div=9
296000 (kHz), mul=37, div=5
203076 (kHz), mul=55, div=12
299076 (kHz), mul=81, div=12

Thanks.

Few words about source code:
1. I'm trying to write Linux kernel module to change ARM core frequency

2. Linux kernel module was written by me from scratch.

3. To compile Linux kernel module I use standard Linux GNU toolchain:
GCC version 4.4.5.

4. You can find source code:
http://git.altlinux.org/people/stanv/packages/dm365.git

5. Code that changes PLL configuration located at file armcore.c, function :
int set_pllrate(struct pll_data *pll, unsigned int prediv, unsigned
int mult, unsigned int postdiv)

Additional information:

Information about environment:
1. TMS320DM365 Rev. E
2. OS Linux, kernel 2.6.34.
3. ARM core attached to PLLC2SYSCLK2.
4. PLLC2SYSCLK2 divider all time is equal to 0 (RATIO=0+1).
5. PLL2 PREDIV all time is equal to 0 (RATIO=0+1).
6. PLLC1SYSCLK4 = 121500 kHz (CFG/DMA bus clock).
7. Oscillator frequency = 24 mHz.
8. Video\Audio codec maybe enabled or disabled.

My algorithm to change ARM core frequency under Linux:
1. Attach  ARM core to PLLC1SYSCLK2 == 243000 Khz.
2. Reset & configure PLL2 for new desired frequency.
3. Attach ARM core back to PLLC2SYSCLK2.

I have tested next frequencies:

122666 (kHz), mul=23, div=8
123428 (kHz), mul=18, div=6
124800 (kHz), mul=13, div=4
125538 (kHz), mul=34, div=12

127058 (kHz), mul=45, div=16
128000 (kHz), mul=8, div=2
129600 (kHz), mul=27, div=9
130285 (kHz), mul=19, div=6
131200 (kHz), mul=41, div=14
132000 (kHz), mul=11, div=3

134400 (kHz), mul=14, div=4
135272 (kHz), mul=31, div=10

137142 (kHz), mul=20, div=6
138000 (kHz), mul=23, div=7
139200 (kHz), mul=29, div=9
140000 (kHz), mul=35, div=11
141000 (kHz), mul=47, div=15
142000 (kHz), mul=71, div=23

145920 (kHz), mul=76, div=24
146823 (kHz), mul=52, div=16
147692 (kHz), mul=40, div=12
148800 (kHz), mul=31, div=9
149333 (kHz), mul=28, div=8
150857 (kHz), mul=22, div=6
151384 (kHz), mul=41, div=12
152000 (kHz), mul=19, div=5
153600 (kHz), mul=16, div=4
154666 (kHz), mul=29, div=8
155076 (kHz), mul=42, div=12
156000 (kHz), mul=13, div=3

159000 (kHz), mul=53, div=15
160000 (kHz), mul=10, div=2
161454 (kHz), mul=37, div=10

163200 (kHz), mul=17, div=4
164571 (kHz), mul=24, div=6

166153 (kHz), mul=45, div=12
167040 (kHz), mul=87, div=24
168000 (kHz), mul=7, div=1
169846 (kHz), mul=46, div=12
170666 (kHz), mul=32, div=8

172800 (kHz), mul=18, div=4
173538 (kHz), mul=47, div=12

175058 (kHz), mul=62, div=16
176000 (kHz), mul=11, div=2
177600 (kHz), mul=37, div=9

179200 (kHz), mul=56, div=14

181333 (kHz), mul=34, div=8
182400 (kHz), mul=19, div=4
183272 (kHz), mul=42, div=10
184000 (kHz), mul=23, div=5
185142 (kHz), mul=27, div=6

187200 (kHz), mul=39, div=9
188000 (kHz), mul=47, div=11
189000 (kHz), mul=63, div=15
190000 (kHz), mul=95, div=23
192000 (kHz), mul=4, div=0
193920 (kHz), mul=101, div=24
194823 (kHz), mul=69, div=16
195692 (kHz), mul=53, div=12
196800 (kHz), mul=41, div=9
197333 (kHz), mul=37, div=8
198857 (kHz), mul=29, div=6
199384 (kHz), mul=54, div=12

202666 (kHz), mul=38, div=8

206400 (kHz), mul=43, div=9
207000 (kHz), mul=69, div=15
208000 (kHz), mul=13, div=2
209454 (kHz), mul=48, div=10
210000 (kHz), mul=35, div=7
211200 (kHz), mul=22, div=4

213333 (kHz), mul=40, div=8
214153 (kHz), mul=58, div=12
215040 (kHz), mul=112, div=24
216000 (kHz), mul=9, div=1
217846 (kHz), mul=59, div=12
218666 (kHz), mul=41, div=8
219428 (kHz), mul=32, div=6
220800 (kHz), mul=23, div=4
221538 (kHz), mul=60, div=12
222000 (kHz), mul=37, div=7
223058 (kHz), mul=79, div=16
224000 (kHz), mul=14, div=2
225600 (kHz), mul=47, div=9
226285 (kHz), mul=33, div=6
227200 (kHz), mul=71, div=14
228000 (kHz), mul=19, div=3
229333 (kHz), mul=43, div=8
230400 (kHz), mul=24, div=4
231272 (kHz), mul=53, div=10

233142 (kHz), mul=34, div=6
234000 (kHz), mul=39, div=7
235200 (kHz), mul=49, div=9
236000 (kHz), mul=59, div=11
237000 (kHz), mul=79, div=15
238000 (kHz), mul=119, div=23
240000 (kHz), mul=5, div=0
241920 (kHz), mul=126, div=24
242823 (kHz), mul=86, div=16
243692 (kHz), mul=66, div=12
244800 (kHz), mul=51, div=9
245333 (kHz), mul=46, div=8
246857 (kHz), mul=36, div=6
247384 (kHz), mul=67, div=12

250666 (kHz), mul=47, div=8
251076 (kHz), mul=68, div=12

253714 (kHz), mul=37, div=6
254400 (kHz), mul=53, div=9
255000 (kHz), mul=85, div=15
256000 (kHz), mul=16, div=2
257454 (kHz), mul=59, div=10
258000 (kHz), mul=43, div=7
259200 (kHz), mul=27, div=4
260571 (kHz), mul=38, div=6
261333 (kHz), mul=49, div=8
262153 (kHz), mul=71, div=12
263040 (kHz), mul=137, div=24
264000 (kHz), mul=11, div=1
265846 (kHz), mul=72, div=12
266666 (kHz), mul=50, div=8
267428 (kHz), mul=39, div=6

269538 (kHz), mul=73, div=12
270000 (kHz), mul=45, div=7
271058 (kHz), mul=96, div=16

273600 (kHz), mul=57, div=9
274285 (kHz), mul=40, div=6
275200 (kHz), mul=86, div=14
276000 (kHz), mul=23, div=3
277333 (kHz), mul=52, div=8

279272 (kHz), mul=64, div=10
280000 (kHz), mul=35, div=5
281142 (kHz), mul=41, div=6
282000 (kHz), mul=47, div=7
283200 (kHz), mul=59, div=9
284000 (kHz), mul=71, div=11
285000 (kHz), mul=95, div=15
286000 (kHz), mul=143, div=23
288000 (kHz), mul=6, div=0
289920 (kHz), mul=151, div=24
290823 (kHz), mul=103, div=16
291692 (kHz), mul=79, div=12
292800 (kHz), mul=61, div=9
293333 (kHz), mul=55, div=8
294857 (kHz), mul=43, div=6
295384 (kHz), mul=80, div=12

298666 (kHz), mul=56, div=8

300000 (kHz), mul=25, div=3

But, works only:

184000 (kHz), mul=23, div=5
185142 (kHz), mul=27, div=6

192000 (kHz), mul=4, div=0
198857 (kHz), mul=29, div=6

208000 (kHz), mul=13, div=2
210000 (kHz), mul=35, div=7
211200 (kHz), mul=22, div=4

216000 (kHz), mul=9, div=1
219428 (kHz), mul=32, div=6
220800 (kHz), mul=23, div=4
224000 (kHz), mul=14, div=2
226285 (kHz), mul=33, div=6
228000 (kHz), mul=19, div=3
230400 (kHz), mul=24, div=4

233142 (kHz), mul=34, div=6
240000 (kHz), mul=5, div=0
246857 (kHz), mul=36, div=6

253714 (kHz), mul=37, div=6
253714 (kHz), mul=37, div=6
256000 (kHz), mul=16, div=2

264000 (kHz), mul=11, div=1

276000 (kHz), mul=23, div=3

288000 (kHz), mul=6, div=0

300000 (kHz), mul=25, div=3

Switch to above frequencies are stable, and works all time.

Why my board hangs on most supported frequencies ?

Thanks!

I have a similar problem, though I am not following the same procedure.
It is explaineds in this thread.

Instead of changing the PLL frequency, only the SYSCLK2 divider is touched.

Frequency below 180 MHz won't work, once code is running from DDR2.
Please note that no other clock is touched, since only the SYSCLK2 divider is touched.
For code running from internal RAM, I am able to go below 180 MHz.

bandini, hello.

Thanks for your suggestion.

But in my case, I need to perform full reset of PLL2, to set new devisor/multiplier values.

Could you share your source code to work with internal RAM ?

Thanks.

Also, it means that time to downgrade ARM core below 180 MHz is quite unstable.

You use Internal RAM to switch bellow 180 MHz, because DDR2 in unstable.

Okey, it seems clever. You can disable all IRQs for that time.

But, I'm confusing about EDMA :(

Can anybody give warranty, that EDMA controller doesn't touch DDR memory at this short period ?

Sorry, I did not mean I switched to RAM and back to DDR2. What I did is play with SYSCLK2 divider.

In kernel, ie with code running from DDR2, only 270 MHz and 180 MHz work

In the bootloader where code is running from RAM, i can run at 135 MHz. But as soon as I run U-boot, which
runs from DDR, It becomes unstable.

The common point between our two situation, is that running below 180 MHz is not working, whether you change
the PLL settings, or the SYSCLK divider.