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AM5748: MMU and Cache Settings for Bare Metal Operation on IDK574x board

KTM
Intellectual 850 points
Part Number: AM5748

Hello,

I have the IDK AM574x development board and I'm trying to understand how to set up the MMU and caching when running bare metal.  I'm using CCS 9.1 and SDK 6_01_00_08.  I have the example in \pdk_am57xx_1_0_16\packages\ti\csl\example\mmu\a15_data_validation  running as a CCS project.  I noticed that the UART is not used unless the MMU is disabled.  What MMU/cache settings do I need to add so that the UART can be used with the MMU enabled?  I made the following changes to mmu_a15_data_validation_app_main.c without success.  The first Puts() works fine but the second does not.  I'm new to this processor.  Can someone end my struggles and provide some guidance? Are there other bare metal examples for the AM574x that address MMU and caching? 

Thanks,

KTM

    uint32_t deviceMemory = 0x48000000;

    UARTConfigPuts(uartBaseAddr,"\r\nA15 MMU Data Validation Test Application", -1);

    /* Check if cache is already enabled */
    cacheEnabled = CACHEA15GetEnabled();

    /* In case cache is disabled, invalidate and enable it */
    if (CACHE_A15_TYPE_ALL != cacheEnabled)
    {
        CACHEA15InvalidateL1DAll();

        CACHEA15InvalidateL1IAll();

        CACHEA15Enable(CACHE_A15_TYPE_ALL);
    }

    /* Initialize MMU module */
    MMUA15Init();


    /* See Tables B4-7 and B4-8 of ARM Architecture Reference Manual for attribute bit values */
    /* 0x00 = Strongly-ordered or Device, non-cacheable
     * 0x44 = Normal memory type, Outer non-cacheable, Inner non-cacheable
     * 0xFF = Normal memory type, Outer write-through cacheable, Inner write-back cacheable
     */
    MMUA15SetMAIR(&gMmuTable, MMU_A15_ATTR_INDEX_0, 0x44); /* Normal memory, non-cacheable */
    MMUA15SetMAIR(&gMmuTable, MMU_A15_ATTR_INDEX_1, 0x00); /* Device (for peripherals), non-cacheable */
    MMUA15SetMAIR(&gMmuTable, MMU_A15_ATTR_INDEX_2, 0xFF); /* Normal memory,  inner and outer cacheable */


    /* Initialize descriptor attributes */
    MMUA15InitDescAttrs(&gAttrs);

    /* Set level one descriptor attributes */
    gAttrs.descriptorType = MMU_A15_DESCRIPTOR_TYPE_BLOCK;
    gAttrs.attrIndx       = MMU_A15_ATTR_INDEX_2;
    gAttrs.nonSecure      = MMU_A15_NON_SECURE_ENABLE;
    gAttrs.accPerm        = MMU_A15_ACC_PERM_RW_ANY_PL; /*Read Write at any PL*/

    /* Set level one descriptor */
    virtualAddr = 0x0, phyAddr = 0x0;
    MMUA15SetFirstLevelDesc(&gMmuTable, virtualAddr, phyAddr, &gAttrs);
    virtualAddr = 0x40000000, phyAddr = 0x40000000;
    MMUA15SetFirstLevelDesc(&gMmuTable, virtualAddr, phyAddr, &gAttrs);
    virtualAddr = 0x80000000, phyAddr = 0x80000000;
    MMUA15SetFirstLevelDesc(&gMmuTable, virtualAddr, phyAddr, &gAttrs);
    virtualAddr = 0xc0000000, phyAddr = 0x80000000;
    MMUA15SetFirstLevelDesc(&gMmuTable, virtualAddr, phyAddr, &gAttrs);


    gAttrs.attrIndx       = MMU_A15_ATTR_INDEX_1;
    gAttrs.noExecute      = TRUE;
    gAttrs.shareable      = MMU_A15_NON_SHAREABLE;
    gAttrs.nonSecure      = MMU_A15_NON_SECURE_DISABLE;
    MMUA15SetSecondLevelDesc(&gMmuTable, deviceMemory, deviceMemory, &gAttrs);

    /* Enable MMU */
    MMUA15Enable(&gMmuTable);

    UARTConfigPuts(uartBaseAddr,"\r\nCache configure 2", -1);

  • 0
    TI__Genius 14680 points

    KTM,

    Please have a look to https://e2e.ti.com/support/processors/f/791/t/579072 , which is a detailed thread discussing MMU/cache configuration for the GPMC interface. I'll look for other examples that may help you get through the initialization.

    Best regards,

    Dave

  • 0 in reply to Dave Bell
    Intellectual 850 points

    Dave,

    Thanks for the response.  I saw that thread earlier but had trouble discerning how the RTOS configures the MMU "behind the scenes" and what I need to do.  I did stumble upon this link that really helped:

    https://e2e.ti.com/support/processors/f/791/p/648308/2387679 

    Below is my updated code.  The second Puts() now works.  Please let me know if I missed something.  I still need to verify that caching working for the OCMC RAM.

    KTM

        UARTConfigPuts(uartBaseAddr,"\r\nCache configure", -1);

        /* Initialize MMU module */
        MMUA15Init();


        /* See Tables B4-7 and B4-8 of ARM Architecture Reference Manual for attribute bit values */
        /* 0x00 = Strongly-ordered or Device, non-cacheable
         * 0x44 = Normal memory type, Outer non-cacheable, Inner non-cacheable
         * 0xFF = Normal memory type, Outer write-through cacheable, Inner write-back cacheable
         */
        MMUA15SetMAIR(&gMmuTable, MMU_A15_ATTR_INDEX_0, 0x44); /* Normal memory, non-cacheable */
        MMUA15SetMAIR(&gMmuTable, MMU_A15_ATTR_INDEX_1, 0x00); /* Device (for peripherals), non-cacheable */
        MMUA15SetMAIR(&gMmuTable, MMU_A15_ATTR_INDEX_2, 0xFF); /* Normal memory,  inner and outer cacheable */


        /* Initialize descriptor attributes */
        MMUA15InitDescAttrs(&gAttrsCB);

        /* Set level one descriptor attributes */
        gAttrsCB.descriptorType = MMU_A15_DESCRIPTOR_TYPE_BLOCK;
        gAttrsCB.attrIndx       = MMU_A15_ATTR_INDEX_2;
        gAttrsCB.nonSecure      = MMU_A15_NON_SECURE_ENABLE;
        gAttrsCB.accPerm        = MMU_A15_ACC_PERM_RW_ANY_PL; /*Read Write at any PL*/

        /* Initialize descriptor attributes */
        MMUA15InitDescAttrs(&gAttrsT);
        gAttrsT.descriptorType = MMU_A15_DESCRIPTOR_TYPE_TABLE;
        gAttrsT.attrIndx       = MMU_A15_ATTR_INDEX_1;
        gAttrsT.noExecute      = TRUE;
        gAttrsT.shareable      = MMU_A15_NON_SHAREABLE;
        gAttrsT.nonSecure      = MMU_A15_NON_SECURE_DISABLE;

        /* Set level one descriptor */
        virtualAddr = 0x0, phyAddr = 0x0;
        MMUA15SetFirstLevelDesc(&gMmuTable, virtualAddr, phyAddr, &gAttrsCB);
        virtualAddr = 0x40000000, phyAddr = 0x40000000;
        MMUA15SetFirstLevelDesc(&gMmuTable, virtualAddr, phyAddr, &gAttrsT);
        virtualAddr = 0x80000000, phyAddr = 0x80000000;
        MMUA15SetFirstLevelDesc(&gMmuTable, virtualAddr, phyAddr, &gAttrsCB);
        virtualAddr = 0xC0000000, phyAddr = 0xC0000000;
        MMUA15SetFirstLevelDesc(&gMmuTable, virtualAddr, phyAddr, &gAttrsCB);

        /* Initialize descriptor attributes */
        MMUA15InitDescAttrs(&gAttrsNcB);
        gAttrsNcB.descriptorType = MMU_A15_DESCRIPTOR_TYPE_BLOCK;
        gAttrsNcB.attrIndx       = MMU_A15_ATTR_INDEX_1;
        gAttrsNcB.noExecute      = TRUE;
        gAttrsNcB.shareable      = MMU_A15_NON_SHAREABLE;
        gAttrsNcB.nonSecure      = MMU_A15_NON_SECURE_DISABLE;

        /* Set level two descriptor attributes */
        /* Set one to one mapping for all locks from 40000000 to 80000000 space.
         * for each 2MB page. Make 40200000 to 40400000 as cachable (index 1 and 2)
         * and others non cachable. */
        phyAddr = 0x40000000;
        for (index = 0;index < MMU_A15_NUM_SECOND_LEVEL_BUFFER_ENTRIES; index++)
        {
            if( index == 1 || index == 2)
            {
                MMUA15SetSecondLevelDesc(&gMmuTable, phyAddr, phyAddr, &gAttrsCB);
            }
            else
            {
                MMUA15SetSecondLevelDesc(&gMmuTable, phyAddr, phyAddr, &gAttrsNcB);
            }
            phyAddr += 0x200000;
        }

        /* Enable MMU */
        MMUA15Enable(&gMmuTable);

        UARTConfigPuts(uartBaseAddr,"\r\nCache configure 2", -1);