Hello,everyone
i meet one question: loading program ..\DM365\NANDWRITER_IPNC_DM365_1.0.0.OUT, and jump out fram: error file loader, data verification failed at address 0x8e000000, please verify target memory and momery map.
i am doubt from the DDR K4T1G164QE-HCE6 with K4T1G164QE-HCF7, so i check the gel file ..\gel_ipnc_dm36x_1.0.0.gel,but i don't know to deal with it, who can help me?
Thanks!
a new learner
and i post the gel file as following:
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*\
Project : DM365 AV&V
File : Dm365_silicon.gel
Purpose : DM365 System initilization function
Desciption : Contains intilization routines
Version Hystory
---------------
Version Date Who Description
1.0 11/?/08 M. Alanis Added CPU 270 & DDR 216Mhz support
1.1 11/24/08 M. Alanis Added CPU 300mhz,297mhz DDR 243Mhz support
1.2 12/04/08 M. Alanis -Align MJCP/HDVICP w/PLL as spec
-added function 'golden_pll_ddr_init_test_297armPLL2_243ddrPLL1_Turbo()'
-added function 'PLLInit_24M_297armPLL2_243ddrPLL1_Turbo();'
-added function 'golden_pll_ddr_init_test_270armPLL2_216ddrPLL1_Normal()'
-added function 'PLLInit_24M__270armPLL2_216ddrPLL1_Normal();'
01/29/10 Appropho -added function 'PLLInit_24M_405armPLL2_340ddrPLL1_Turbo()
-removed some functions
/* AEMIF CFG SPACE */
/*system regs*/
#define AEMIF_CFG_ADDR 0x01D10000
#define AEMIF_CS2_BASE_ADDR 0x02000000
#define AEMIF_CS3_BASE_ADDR 0x04000000
#define RCSR (unsigned int*)(AEMIF_CFG_ADDR + 0x00) //Revision Code and Status Register
#define WAITCFG (unsigned int*)(AEMIF_CFG_ADDR + 0x04) //Async Wait Cycle Config Register
#define ACFG2 (unsigned int*)(AEMIF_CFG_ADDR + 0x10) //Async Bank1 Config Register
#define ACFG3 (unsigned int*)(AEMIF_CFG_ADDR + 0x14) //Async Bank2 Config Register
#define AINTRAW (unsigned int*)(AEMIF_CFG_ADDR + 0x40) //Interrpt Raw Register
#define AINTMASK (unsigned int*)(AEMIF_CFG_ADDR + 0x44) //Interrupt Masked Register
#define AINTMASKSET (unsigned int*)(AEMIF_CFG_ADDR + 0x48) //Interrupt Mask Set Register
#define INTMASKCLEAR (unsigned int*)(AEMIF_CFG_ADDR + 0x4C) //Interrupt Mask Clear Register
#define NANDCTL (unsigned int*)(AEMIF_CFG_ADDR + 0x60) //NAND Flash Control Register
#define NANDSTAT (unsigned int*)(AEMIF_CFG_ADDR + 0x64) //NAND Flash Status Register
#define NANDECC2 (unsigned int*)(AEMIF_CFG_ADDR + 0x70) //NAND Flash 1 ECC Register
#define NANDECC3 (unsigned int*)(AEMIF_CFG_ADDR + 0x74) //NAND Flash 2 ECC Register
#define NANDECC4 (unsigned int*)(AEMIF_CFG_ADDR + 0x78) //NAND Flash 3 ECC Register
#define NANDECC5 (unsigned int*)(AEMIF_CFG_ADDR + 0x7C) //NAND Flash 4 ECC Register
/* DDR CFG SPACE */
#define DDR_CFG_ADDR 0x20000000
#define DDR_BASE_ADDR 0x80000000
#define DDR_PHY_VTP_IOCTRL (unsigned int *) (0x01C40074 ) // DDR PHY VTP adjust (Read only)
#define EIDRR (unsigned int*)(DDR_CFG_ADDR + 0x00) //EMIF Module ID and Revision Register
#define SDSTAT (unsigned int*)(DDR_CFG_ADDR + 0x04) //SDRAM Status Register
#define SDCFG1 (unsigned int*)(DDR_CFG_ADDR + 0x08) //SDRAM Bank Config Register
#define SDREF (unsigned int*)(DDR_CFG_ADDR + 0x0C) //SDRAM Refresh Control Register
#define SDTIM0 (unsigned int*)(DDR_CFG_ADDR + 0x10) //SDRAM Timing Register
#define SDTIM1 (unsigned int*)(DDR_CFG_ADDR + 0x14) //SDRAM Timing Register
#define SDCFG2 (unsigned int*)(DDR_CFG_ADDR + 0x1C) //SDRAM Config Register 2
#define VBUSMP (unsigned int*)(DDR_CFG_ADDR + 0x20) //VBUSM Burst Priority Register
#define VBUSMCFG1 (unsigned int*)(DDR_CFG_ADDR + 0x28) //VBUSM config Value1 Register
#define VBUSMCFG2 (unsigned int*)(DDR_CFG_ADDR + 0x2c) //VBUSM config Value2 Register
#define INTRAW (unsigned int*)(DDR_CFG_ADDR + 0xC0) //Interrupt Raw Register
#define INTMASK (unsigned int*)(DDR_CFG_ADDR + 0xC4) //Interrupt Masked Register
#define INTMASKSET (unsigned int*)(DDR_CFG_ADDR + 0xC8) //Interrupt Mask Set Register
#define INTMASKCLR (unsigned int*)(DDR_CFG_ADDR + 0xCC) //Interrupt Mask Clear Register
#define DDRPHYREV (unsigned int*)(DDR_CFG_ADDR + 0xE0) //DDR PHY ID and Revision Register
#define DDRPHYCTL1 (unsigned int*)(DDR_CFG_ADDR + 0xE4) //DDR PHY Control 1 Register
#define DDRPHYCTL2 (unsigned int*)(DDR_CFG_ADDR + 0xE8) //DDR PHY Control 2 Register
//Device Configuration Registers
#define SYSCTL_BASE 0x01c40000
#define PERI_CLKCTL (unsigned int *)0x01C40048
#define PLLCFG0 (unsigned int *)0x01C40084
#define PLLCFG1 (unsigned int *)0x01C40088
#define HDIMCOPBT (unsigned int *)0x01C40080
/* Pin MUX Configuration Registers */
#define PINMUX0 (unsigned int *)0x01C40000
#define PINMUX1 (unsigned int *)0x01C40004
#define PINMUX2 (unsigned int *)0x01C40008
#define PINMUX3 (unsigned int *)0x01C4000C
#define PINMUX4 (unsigned int *)0x01C40010
//MJCP Config Base Address
#define CONFIG_BASE 0x01ca0000 // MJCP Base Address
/* PLL1 base address */
#define PLL1_BASE 0x01C40800
#define PLL1_PLLCTL (unsigned int *)(PLL1_BASE+ 0x100)
#define PLL1_SECCTL (unsigned int *)(PLL1_BASE+ 0x108)
#define PLL1_PLLM (unsigned int *)(PLL1_BASE+ 0x110)
#define PLL1_PREDIV (unsigned int *)(PLL1_BASE+ 0x114)
#define PLL1_PLLDIV1 (unsigned int *)(PLL1_BASE+ 0x118)
#define PLL1_PLLDIV2 (unsigned int *)(PLL1_BASE+ 0x11C)
#define PLL1_PLLDIV3 (unsigned int *)(PLL1_BASE+ 0x120)
#define PLL1_OSCDIV1 (unsigned int *)(PLL1_BASE+ 0x124)
#define PLL1_POSTDIV (unsigned int *)(PLL1_BASE+ 0x128)
#define PLL1_BPDIV (unsigned int *)(PLL1_BASE+ 0x12C)
#define PLL1_PLLCMD (unsigned int *)(PLL1_BASE+ 0x138)
#define PLL1_PLLSTAT (unsigned int *)(PLL1_BASE+ 0x13C)
#define PLL1_PLLDIV4 (unsigned int *)(PLL1_BASE+ 0x160)
#define PLL1_PLLDIV5 (unsigned int *)(PLL1_BASE+ 0x164)
#define PLL1_PLLDIV6 (unsigned int *)(PLL1_BASE+ 0x168)
#define PLL1_PLLDIV7 (unsigned int *)(PLL1_BASE+ 0x16c)
#define PLL1_PLLDIV8 (unsigned int *)(PLL1_BASE+ 0x170)
#define PLL1_PLLDIV9 (unsigned int *)(PLL1_BASE+ 0x174)
/* PLL2 base address */
#define PLL2_BASE 0x01C40C00
#define PLL2_PLLCTL (unsigned int *)(PLL2_BASE+ 0x100)
#define PLL2_SECCTL (unsigned int *)(PLL2_BASE+ 0x108)
#define PLL2_PLLM (unsigned int *)(PLL2_BASE+ 0x110)
#define PLL2_PREDIV (unsigned int *)(PLL2_BASE+ 0x114)
#define PLL2_PLLDIV1 (unsigned int *)(PLL2_BASE+ 0x118)
#define PLL2_PLLDIV2 (unsigned int *)(PLL2_BASE+ 0x11C)
#define PLL2_PLLDIV3 (unsigned int *)(PLL2_BASE+ 0x120)
#define PLL2_OSCDIV1 (unsigned int *)(PLL2_BASE+ 0x124)
#define PLL2_POSTDIV (unsigned int *)(PLL2_BASE+ 0x128)
#define PLL2_BPDIV (unsigned int *)(PLL2_BASE+ 0x12C)
#define PLL2_PLLCMD (unsigned int *)(PLL2_BASE+ 0x138)
#define PLL2_PLLSTAT (unsigned int *)(PLL2_BASE+ 0x13C)
#define PLL2_PLLDIV4 (unsigned int *)(PLL2_BASE+ 0x160)
#define PLL2_PLLDIV5 (unsigned int *)(PLL2_BASE+ 0x164)
//PSC
#define LPSC_EDMA_CC 0
#define LPSC_EDMA_TC0 1
#define LPSC_EDMA_TC1 2
#define LPSC_EDMA_TC2 3
#define LPSC_EDMA_TC3 4
#define LPSC_DDR_EMIF 13
#define LPSC_AEMIF 14
#define LPSC_UART0 19
#define LPSC_UART1 20
#define LPSC_MJCP 50
#define LPSC_HDVICP 51
#define PSC_ADDR 0x01C41000
#define EPCPR (unsigned int *)(PSC_ADDR+0x070)
#define PTCMD (unsigned int *)(PSC_ADDR+0x120)
#define PTSTAT (unsigned int *)(PSC_ADDR+0x128)
#define PDSTAT (unsigned int *)(PSC_ADDR+0x200)
#define PDSTAT1 (unsigned int *)(PSC_ADDR+0x204)
#define PDCTL (unsigned int *)(PSC_ADDR+0x300)
#define PDCTL1 (unsigned int *)(PSC_ADDR+0x304)
#define MDSTAT_DDR (unsigned int *)(PSC_ADDR+0x800+4*LPSC_DDR_EMIF)
#define MDCTL_DDR (unsigned int *)(PSC_ADDR+0xA00+4*LPSC_DDR_EMIF)
#define MDSTAT_AEMIF (unsigned int *)(PSC_ADDR+0x800+4*LPSC_AEMIF)
#define MDCTL_AEMIF (unsigned int *)(PSC_ADDR+0xA00+4*LPSC_AEMIF)
#define MDSTAT_EDMA_CC (unsigned int *)(PSC_ADDR+0x800+4*LPSC_EDMA_CC)
#define MDCTL_EDMA_CC (unsigned int *)(PSC_ADDR+0xA00+4*LPSC_EDMA_CC)
#define MDSTAT_EDMA_TC0 (unsigned int *)(PSC_ADDR+0x800+4*LPSC_EDMA_TC0)
#define MDCTL_EDMA_TC0 (unsigned int *)(PSC_ADDR+0xA00+4*LPSC_EDMA_TC0)
#define MDSTAT_EDMA_TC1 (unsigned int *)(PSC_ADDR+0x800+4*LPSC_EDMA_TC1)
#define MDCTL_EDMA_TC1 (unsigned int *)(PSC_ADDR+0xA00+4*LPSC_EDMA_TC1)
#define MDSTAT_EDMA_TC2 (unsigned int *)(PSC_ADDR+0x800+4*LPSC_EDMA_TC2)
#define MDCTL_EDMA_TC2 (unsigned int *)(PSC_ADDR+0xA00+4*LPSC_EDMA_TC2)
#define MDSTAT_EDMA_TC3 (unsigned int *)(PSC_ADDR+0x800+4*LPSC_EDMA_TC3)
#define MDCTL_EDMA_TC3 (unsigned int *)(PSC_ADDR+0xA00+4*LPSC_EDMA_TC3)
#define MDSTAT_MJCP (unsigned int *)(PSC_ADDR+0x800+4*LPSC_MJCP)
#define MDCTL_MJCP (unsigned int *)(PSC_ADDR+0xA00+4*LPSC_MJCP)
#define MDSTAT_HDVICP (unsigned int *)(PSC_ADDR+0x800+4*LPSC_HDVICP)
#define MDCTL_HDVICP (unsigned int *)(PSC_ADDR+0xA00+4*LPSC_HDVICP)
#define MDSTAT_UART0 (unsigned int *)(PSC_ADDR+0x800+4*LPSC_UART0)
#define MDCTL_UART0 (unsigned int *)(PSC_ADDR+0xA00+4*LPSC_UART0)
#define MDSTAT_UART1 (unsigned int *)(PSC_ADDR+0x800+4*LPSC_UART1)
#define MDCTL_UART1 (unsigned int *)(PSC_ADDR+0xA00+4*LPSC_UART1)
hotmenu golden_pll_ddr_init_test_405armPLL2_340ddrPLL1_DM368()
{
//Enable all module clocks
DM365_PSCEnableAll();
//Configure Pin Multiplexing
Setup_Pin_Mux();
///* Wiggle I2C clock line to make sure devices aren't hung */
I2C_GPIO_pin_prime();
//Initiailzes the DDR2 PHY
DDR2_VTP_Init();
//setup PLL1 and PLL2, Assuming PLL Mult works the setup is for ARM300 and DDR 243Mhz
//clock dividers are properly setup for all system clock domains
PLLInit_24M_405armPLL2_340ddrPLL1_Turbo();
//Setup DDR2 timing parameters for DDR 243Mhz but will work for lower DDR speed settings
DDR16bitInit_340Mhz_test();
}
hotmenu golden_pll_ddr_init_test_297armPLL2_270ddrPLL1_Turbo()
{
//Enable all module clocks
DM365_PSCEnableAll();
//Configure Pin Multiplexing
Setup_Pin_Mux();
///* Wiggle I2C clock line to make sure devices aren't hung */
I2C_GPIO_pin_prime();
//Initiailzes the DDR2 PHY
DDR2_VTP_Init();
//setup PLL1 and PLL2, Assuming PLL Mult works the setup is for ARM300 and DDR 243Mhz
//clock dividers are properly setup for all system clock domains
PLLInit_24M_297armPLL2_270ddrPLL1_Turbo();
//Setup DDR2 timing parameters for DDR 243Mhz but will work for lower DDR speed settings
DDR16bitInit_270Mhz_test();
}
hotmenu golden_pll_ddr_init_test_270armPLL2_216ddrPLL1_Normal()
{
//Enable all module clocks
DM365_PSCEnableAll();
//Configure Pin Multiplexing
Setup_Pin_Mux();
///* Wiggle I2C clock line to make sure devices aren't hung */
I2C_GPIO_pin_prime();
//Initiailzes the DDR2 PHY
DDR2_VTP_Init();
//setup PLL1 and PLL2, Assuming PLL Mult works the setup is for ARM300 and DDR 243Mhz
//clock dividers are properly setup for all system clock domains
PLLInit_24M__270armPLL2_216ddrPLL1_Normal();
//Setup DDR2 timing parameters for DDR 216Mhz but will work for lower DDR speed settings
DDR16bitInit_216Mhz_test();
}
//Enables the clock for all modules in DM365
//------------------------------------------------------------
DM365_PSCEnableAll()
{
unsigned char i=0;
unsigned char lpsc_start;
unsigned char lpsc_end,lpscgroup,lpscmin,lpscmax;
unsigned int domainOn=0, PdNum = 0;
lpscmin =0;
lpscmax =2;
for(lpscgroup=lpscmin ; lpscgroup <=lpscmax; lpscgroup++) {
if(lpscgroup==0)
{
lpsc_start = 0; // Enabling LPSC 3 to 28 SCR first
lpsc_end = 28;
}
else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
lpsc_start = 38;
lpsc_end = 47;
} else {
lpsc_start = 50;
lpsc_end = 51;
}
//NEXT=0x3, Enable LPSC's
for(i=lpsc_start; i<=lpsc_end; i++) {
// CSL_FINS(CSL_PSC_0_REGS->MDCTL[i], PSC_MDCTL_NEXT, 0x3);
*((PSC_ADDR+0xA00+(4*i))) |= 0x3;
}
//Program goctl to start transition sequence for LPSCs
//CSL_PSC_0_REGS->PTCMD = (1<<PdNum); /*Kick off Power Domain 0 Modules*/
*PTCMD = (1<<PdNum);
//Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
//while(! (((CSL_PSC_0_REGS->PTSTAT >> PdNum) & 0x00000001) == 0));
while(! (((*PTSTAT >> PdNum) & 0x00000001) == 0));
//Wait for MODSTAT = ENABLE from LPSC's
for(i=lpsc_start; i<=lpsc_end; i++) {
// while(!((CSL_PSC_0_REGS->MDSTAT[i] & 0x0000001F) == 0x3));
while(!((*(PSC_ADDR+0x800+(4*i)) & 0x0000001F) == 0x3));
}
}
GEL_TextOut("\n DM365 all Module Clocks are Turned on\n");
}
//Initiailzes the DDR2 PHY
//---------------------------------
DDR2_VTP_Init()
{
// VTP Caliberation
//PWR_DWN bit is made '0', to power the VTP module
*(DDR_PHY_VTP_IOCTRL) = (*(DDR_PHY_VTP_IOCTRL)) & 0xFFFF9F3F;
// Set bit CLRZ (bit 13)
*(DDR_PHY_VTP_IOCTRL) = (*(DDR_PHY_VTP_IOCTRL)) | 0x00002000;
// Check VTP READY Status
while( !(*DDR_PHY_VTP_IOCTRL & 0x8000));
// Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
//*(DDR_PHY_VTP_IOCTRL) = *(DDR_PHY_VTP_IOCTRL) | 0x00004000;
// Set bit LOCK(bit7) and PWRSAVE (bit8)
*(DDR_PHY_VTP_IOCTRL) = *(DDR_PHY_VTP_IOCTRL) | 0x00000080;
// Powerdown VTP as it is locked (bit 6)
// Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
*(DDR_PHY_VTP_IOCTRL) = *(DDR_PHY_VTP_IOCTRL) | 0x00004040;
GEL_TextOut("DDR2 VTP Init is done\n");
}
PLLInit_24M_405armPLL2_340ddrPLL1_Turbo()
{
unsigned int j;
unsigned int lock_status= 0x0;
unsigned int CLKSRC=0x1; /*CLKSRC=1 =>External Oscilator
CLKSRC=0 => Onchip oscilator */
GEL_TextOut("Please wait PLL1 &PLL2 initialization is in Progress........\n");
// Program PERI_CLKCTL for PLL selection for ARM,DDR,HDVICP ARM
// DDR, HDVICP on PLL1,
// ARM926, HDVICP(ARM968) on PLL2
// Info from PERI_CLKCTL register:
// Key Scan = PLLC1_AUXCLK / (PLLDIV3+1)
// Voice Codec = PLLC2_SYSCLK4 / (PLLDIV2+1)
*PERI_CLKCTL = 0x243F0FFC;
/*Power up the PLL*/
*PLL1_PLLCTL &= 0xFFFFFFFD;
/*Disable the PLL*/
*PLL1_PLLCTL |= 0x10;
/*Bring the PLL out of Disable Mode*/
*PLL1_PLLCTL &= 0xFFFFFFEF;
/*Select the Clock Mode as Onchip Oscilator or External Clock on MXI pin*/
/*VDB has input on MXI pin */
*PLL1_PLLCTL &= 0xFFFFFEFF;
*PLL1_PLLCTL |= CLKSRC<<8;
/*Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR*/
*PLL1_PLLCTL &= 0xFFFFFFDF;
/*Set PLLEN=0 => PLL BYPASS MODE*/
*PLL1_PLLCTL &= 0xFFFFFFFE;
/*Wait at least 4 MXI clock or referene clock cycles to allow PLLEN mux switches properly to bypass clock*/
for(j=0; j<0x20; j++) {}
// PLLRST=1(reset assert)
*PLL1_PLLCTL |= 0x00000008;
/*Disable the PLL*/
*PLL1_PLLCTL |= 0x10;
/*Power up the PLL*/
*PLL1_PLLCTL &= 0xFFFFFFFD;
/*Bring the PLL out of Disable Mode*/
*PLL1_PLLCTL &= 0xFFFFFFEF;
/*Bring PLL out of Reset*/
*PLL1_PLLCTL &= 0xFFFFFFF7; //added for testpurpose:uvj
//Program the Multiper and Pre-Divider for PLL1
*PLL1_PLLM = 85; // M=85 ; VCO will 24*2M/N+1 = 680Mhz
*PLL1_PREDIV = 0x8000|0x5; // N = 5
*PLL1_SECCTL = 0x00470000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1
*PLL1_SECCTL = 0x00460000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0
*PLL1_SECCTL = 0x00400000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0
*PLL1_SECCTL = 0x00410000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1
//Program the PostDiv for PLL1
*PLL1_POSTDIV = 0x8000;
// Post divider setting for PLL1
// *PLL1_PLLDIV1 = 0x8xxx; // POST DIV USB Alternate current setting will not yield 24Mhz use PLL1 AUXclk
*PLL1_PLLDIV3 = 0x8001; // POST DIV 680/2 = 340Mhz -> MJCP/HDVICP
*PLL1_PLLDIV4 = 0x8003; // POST DIV 680/4 = 170Mhz -> EDMA/Peripheral CFG0
*PLL1_PLLDIV5 = 0x8001; // POST DIV 680/2 = 340Mhz -> VPSS
// *PLL1_PLLDIV6 = 0x8011; // POST DIV 680/18 = 27Mhz -> VENC alternate for SD
*PLL1_PLLDIV7 = 0x8000; // POST DIV 680/2 = 340Mhz -> DDR
*PLL1_PLLDIV8 = 0x800D; // POST DIV 680/14= 48.6Mhz-> MMC0/SD0
*PLL1_PLLDIV9 = 0x801B; // POST DIV 680/28 = 24.3Mhz-> CLKOUT
for(j=0; j<0x100; j++) {} /*Wait for PLL to Reset properly=>PLL reset Time = at least 5us*/
/*Set the GOSET bit */
*PLL1_PLLCMD = 0x00000001; // Go
/*Wait for PLL to LOCK */
while(! (((*PLLCFG0) & 0x07000000) == 0x07000000));
/*Enable the PLL Bit of PLLCTL*/
*PLL1_PLLCTL |= 0x00000001; // PLLEN=0
GEL_TextOut("Turbo Mode:: PLL1:486Mhz enabled\n");
/****************PLL2 ********************************/
GEL_TextOut("Please wait PLL2 initialization is in Progress........\n");
/*Power up the PLL*/
*PLL2_PLLCTL &= 0xFFFFFFFD;
/*Disable the PLL*/
*PLL2_PLLCTL |= 0x10;
/*Bring the PLL out of Disable Mode*/
*PLL2_PLLCTL &= 0xFFFFFFEF;
/*Select the Clock Mode as Onchip Oscilator or External Clock on MXI pin*/
/*VDB has input on MXI pin */
*PLL2_PLLCTL &= 0xFFFFFEFF;
*PLL2_PLLCTL |= CLKSRC<<8;
/*Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR*/
*PLL2_PLLCTL &= 0xFFFFFFDF;
/*Set PLLEN=0 => PLL BYPASS MODE*/
*PLL2_PLLCTL &= 0xFFFFFFFE;
/*Wait at least 4 MXI clock or referene clock cycles to allow PLLEN mux switches properly to bypass clock*/
for(j=0; j<0x20; j++) {}
// PLLRST=1(reset assert)
*PLL2_PLLCTL |= 0x00000008;
for(j=0; j<0x100; j++) {} //added for testpurpose:uvj
/*Bring PLL out of Reset*/
*PLL2_PLLCTL &= 0xFFFFFFF7;
//Program the Multiper and Pre-Divider for PLL2
*PLL2_PLLM = 135; // M=135; VCO will 24*2M/N+1 = 405Mhz
*PLL2_PREDIV = 0x8000| 0xF; // N = 15
*PLL2_POSTDIV = 0x8000; // div by 1
*PLL2_SECCTL = 0x00470000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1
*PLL2_SECCTL = 0x00460000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0
*PLL2_SECCTL = 0x00400000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0
*PLL2_SECCTL = 0x00410000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1
// Post divider setting for PLL2
// *PLL2_PLLDIV1 = 0x8xxx; // POST DIV USB Alternate current setting will not yield 24Mhz use PLL1 AUXclk
*PLL2_PLLDIV2 = 0x8000; // POST DIV 405/1=405 Mhz -> ARM926/HDVICP Cont
// *PLL2_PLLDIV3 = 0x8xxx; // DDR 2X clk Alternate, used PLL1 for Turbo mode
*PLL2_PLLDIV4 = 0x800A; // POST DIV 405/11= 36.82 Mhz->VOICE
*PLL2_PLLDIV5 = 0x800E; // POST DIV 405/15=27 Mhz -> VENC for SD video
//GoCmd for PostDivider to take effect
*PLL2_PLLCMD = 0x00000001;
/*Wait for PLL to LOCK */
while(! (((*PLLCFG1) & 0x07000000) == 0x07000000));
//Enable the PLL2
*PLL2_PLLCTL |= 0x00000001; // PLLEN=0
*PERI_CLKCTL &= 0xFFFFFFFB; //Enable CLKOUT2 driver
*PINMUX4 |= 0x300; //GIO31 will act as CLKOUT2
GEL_TextOut("Turbo Mode:: PLL2:594Mhz enabled\n");
}
PLLInit_24M_297armPLL2_270ddrPLL1_Turbo()
{
unsigned int j;
unsigned int lock_status= 0x0;
unsigned int CLKSRC=0x1; /*CLKSRC=1 =>External Oscilator
CLKSRC=0 => Onchip oscilator */
GEL_TextOut("Please wait PLL1 &PLL2 initialization is in Progress........\n");
// Program PERI_CLKCTL for PLL selection for ARM,DDR,HDVICP ARM
// DDR, HDVICP on PLL1,
// ARM926, HDVICP(ARM968) on PLL2
// Info from PERI_CLKCTL register:
// Key Scan = PLLC1_AUXCLK / (PLLDIV3+1)
// Voice Codec = PLLC2_SYSCLK4 / (PLLDIV2+1)
*PERI_CLKCTL = 0x243F0FFC;
/*Power up the PLL*/
*PLL1_PLLCTL &= 0xFFFFFFFD;
/*Disable the PLL*/
*PLL1_PLLCTL |= 0x10;
/*Bring the PLL out of Disable Mode*/
*PLL1_PLLCTL &= 0xFFFFFFEF;
/*Select the Clock Mode as Onchip Oscilator or External Clock on MXI pin*/
/*VDB has input on MXI pin */
*PLL1_PLLCTL &= 0xFFFFFEFF;
*PLL1_PLLCTL |= CLKSRC<<8;
/*Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR*/
*PLL1_PLLCTL &= 0xFFFFFFDF;
/*Set PLLEN=0 => PLL BYPASS MODE*/
*PLL1_PLLCTL &= 0xFFFFFFFE;
/*Wait at least 4 MXI clock or referene clock cycles to allow PLLEN mux switches properly to bypass clock*/
for(j=0; j<0x20; j++) {}
// PLLRST=1(reset assert)
*PLL1_PLLCTL |= 0x00000008;
/*Disable the PLL*/
*PLL1_PLLCTL |= 0x10;
/*Power up the PLL*/
*PLL1_PLLCTL &= 0xFFFFFFFD;
/*Bring the PLL out of Disable Mode*/
*PLL1_PLLCTL &= 0xFFFFFFEF;
/*Bring PLL out of Reset*/
*PLL1_PLLCTL &= 0xFFFFFFF7; //added for testpurpose:uvj
//Program the Multiper and Pre-Divider for PLL1
*PLL1_PLLM = 90; // M=90 ; VCO will 24*2M/N+1 = 540Mhz
*PLL1_PREDIV = 0x8000|0x7; // N = 7
*PLL1_SECCTL = 0x00470000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1
*PLL1_SECCTL = 0x00460000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0
*PLL1_SECCTL = 0x00400000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0
*PLL1_SECCTL = 0x00410000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1
//Program the PostDiv for PLL1
*PLL1_POSTDIV = 0x8000;
// Post divider setting for PLL1
// *PLL1_PLLDIV1 = 0x8xxx; // POST DIV USB Alternate current setting will not yield 24Mhz use PLL1 AUXclk
*PLL1_PLLDIV3 = 0x8001; // POST DIV 540/2 = 270Mhz -> MJCP/HDVICP
*PLL1_PLLDIV4 = 0x8003; // POST DIV 540/4 = 121.5Mhz -> EDMA/Peripheral CFG0
*PLL1_PLLDIV5 = 0x8001; // POST DIV 540/2 = 270Mhz -> VPSS
*PLL1_PLLDIV6 = 0x8013; // POST DIV 540/20 = 27Mhz -> VENC alternate for SD
*PLL1_PLLDIV7 = 0x8000; // POST DIV 540/2 = 270Mhz -> DDR
*PLL1_PLLDIV8 = 0x8003; // POST DIV 540/4 -> MMC0/SD0
*PLL1_PLLDIV9 = 0x8001; // POST DIV 540/2 -> CLKOUT
for(j=0; j<0x100; j++) {} /*Wait for PLL to Reset properly=>PLL reset Time = at least 5us*/
/*Set the GOSET bit */
*PLL1_PLLCMD = 0x00000001; // Go
/*Wait for PLL to LOCK */
while(! (((*PLLCFG0) & 0x07000000) == 0x07000000));
/*Enable the PLL Bit of PLLCTL*/
*PLL1_PLLCTL |= 0x00000001; // PLLEN=0
GEL_TextOut("Turbo Mode:: PLL1:486Mhz enabled\n");
/****************PLL2 ********************************/
GEL_TextOut("Please wait PLL2 initialization is in Progress........\n");
/*Power up the PLL*/
*PLL2_PLLCTL &= 0xFFFFFFFD;
/*Disable the PLL*/
*PLL2_PLLCTL |= 0x10;
/*Bring the PLL out of Disable Mode*/
*PLL2_PLLCTL &= 0xFFFFFFEF;
/*Select the Clock Mode as Onchip Oscilator or External Clock on MXI pin*/
/*VDB has input on MXI pin */
*PLL2_PLLCTL &= 0xFFFFFEFF;
*PLL2_PLLCTL |= CLKSRC<<8;
/*Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR*/
*PLL2_PLLCTL &= 0xFFFFFFDF;
/*Set PLLEN=0 => PLL BYPASS MODE*/
*PLL2_PLLCTL &= 0xFFFFFFFE;
/*Wait at least 4 MXI clock or referene clock cycles to allow PLLEN mux switches properly to bypass clock*/
for(j=0; j<0x20; j++) {}
// PLLRST=1(reset assert)
*PLL2_PLLCTL |= 0x00000008;
for(j=0; j<0x100; j++) {} //added for testpurpose:uvj
/*Bring PLL out of Reset*/
*PLL2_PLLCTL &= 0xFFFFFFF7;
//Program the Multiper and Pre-Divider for PLL2
*PLL2_PLLM = 0x63; // M=99 ; VCO will 24*2M/N+1 = 594Mhz
*PLL2_PREDIV = 0x8000|0x7; // N = 7
*PLL2_POSTDIV = 0x8000; // div by 1
*PLL2_SECCTL = 0x00470000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1
*PLL2_SECCTL = 0x00460000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0
*PLL2_SECCTL = 0x00400000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0
*PLL2_SECCTL = 0x00410000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1
// Post divider setting for PLL2
// *PLL2_PLLDIV1 = 0x8xxx; // POST DIV USB Alternate current setting will not yield 24Mhz use PLL1 AUXclk
*PLL2_PLLDIV2 = 0x8001; // POST DIV 594/2=297mhz -> ARM926/ARM968
// *PLL2_PLLDIV3 = 0x8xxx; // DDR 2X clk Alternate, used PLL1 for Turbo mode
*PLL2_PLLDIV4 = 0x8005; // POST DIV 594/6 ->VOICE
*PLL2_PLLDIV5 = 0x8007; // POST DIV 594/8=74.25Mhz -> VENC for HD video
// *PLL2_PLLDIV5 = 0x8015; // POST DIV 594/22= 27Mhz -> VENC for SD video
//GoCmd for PostDivider to take effect
*PLL2_PLLCMD = 0x00000001;
/*Wait for PLL to LOCK */
while(! (((*PLLCFG1) & 0x07000000) == 0x07000000));
//Enable the PLL2
*PLL2_PLLCTL |= 0x00000001; // PLLEN=0
*PERI_CLKCTL &= 0xFFFFFFFB; //Enable CLKOUT2 driver
*PINMUX4 |= 0x300; //GIO31 will act as CLKOUT2
GEL_TextOut("Turbo Mode:: PLL2:594Mhz enabled\n");
}
PLLInit_24M__270armPLL2_216ddrPLL1_Normal()
{
unsigned int j;
unsigned int lock_status= 0x0;
unsigned int CLKSRC=0x1; /*CLKSRC=1 =>External Oscilator
CLKSRC=0 => Onchip oscilator */
GEL_TextOut("Please wait PLL1 &PLL2 initialization is in Progress........\n");
// Program PERI_CLKCTL for PLL selection for ARM,DDR,HDVICP ARM
// DDR, HDVICP on PLL1,
// ARM926, HDVICP(ARM968) on PLL2
// Info from PERI_CLKCTL register:
// Key Scan = PLLC1_AUXCLK / (PLLDIV3+1)
// Voice Codec = PLLC2_SYSCLK4 / (PLLDIV2+1)
*PERI_CLKCTL = 0x243F0FFC;
/*Power up the PLL*/
*PLL1_PLLCTL &= 0xFFFFFFFD;
/*Disable the PLL*/
*PLL1_PLLCTL |= 0x10;
/*Bring the PLL out of Disable Mode*/
*PLL1_PLLCTL &= 0xFFFFFFEF;
/*Select the Clock Mode as Onchip Oscilator or External Clock on MXI pin*/
/*VDB has input on MXI pin */
*PLL1_PLLCTL &= 0xFFFFFEFF;
*PLL1_PLLCTL |= CLKSRC<<8;
/*Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR*/
*PLL1_PLLCTL &= 0xFFFFFFDF;
/*Set PLLEN=0 => PLL BYPASS MODE*/
*PLL1_PLLCTL &= 0xFFFFFFFE;
/*Wait at least 4 MXI clock or referene clock cycles to allow PLLEN mux switches properly to bypass clock*/
for(j=0; j<0x20; j++) {}
// PLLRST=1(reset assert)
*PLL1_PLLCTL |= 0x00000008;
/*Disable the PLL*/
*PLL1_PLLCTL |= 0x10;
/*Power up the PLL*/
*PLL1_PLLCTL &= 0xFFFFFFFD;
/*Bring the PLL out of Disable Mode*/
*PLL1_PLLCTL &= 0xFFFFFFEF;
/*Bring PLL out of Reset*/
*PLL1_PLLCTL &= 0xFFFFFFF7; //added for testpurpose:uvj
//Program the Multiper and Pre-Divider for PLL1
*PLL1_PLLM = 0x9; // M=9 ; VCO will 24*2M/N+1 = 432Mhz
*PLL1_PREDIV = 0x8000|0x0; // N = 0
*PLL1_SECCTL = 0x00470000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1
*PLL1_SECCTL = 0x00460000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0
*PLL1_SECCTL = 0x00400000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0
*PLL1_SECCTL = 0x00410000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1
//Program the PostDiv for PLL1
*PLL1_POSTDIV = 0x8000;
//Post divider setting for PLL1
// *PLL1_PLLDIV1 = 0x8xxx; // POST DIV USB Alternate current setting will not yield 24Mhz use PLL1 AUXclk
*PLL1_PLLDIV3 = 0x8001; // POST DIV 432/2 = 216Mhz -> MJCP/HDVICP
*PLL1_PLLDIV4 = 0x8003; // POST DIV 432/4 = 108Mhz -> EDMA/Peripheral CFG0
*PLL1_PLLDIV5 = 0x8001; // POST DIV 432/2 = 216Mhz -> VPSS
// *PLL1_PLLDIV6 = 0x800f; // POST DIV 432/16 = 27Mhz -> VENC alternate for SD
*PLL1_PLLDIV7 = 0x8000; // POST DIV 432/2 = 216Mhz -> DDR
*PLL1_PLLDIV8 = 0x8003; // POST DIV 432/4 -> MMC0/SD0
*PLL1_PLLDIV9 = 0x8001; // POST DIV 432/2 -> CLKOUT
for(j=0; j<0x100; j++) {} /*Wait for PLL to Reset properly=>PLL reset Time = at least 5us*/
/*Set the GOSET bit */
*PLL1_PLLCMD = 0x00000001; // Go
/*Wait for PLL to LOCK */
while(! (((*PLLCFG0) & 0x07000000) == 0x07000000));
// for(j=0;j<1000;j++) /*Wait for PLL to LOCK atleast 8000 MXI clock or Reference clock cycles*/
/*Enable the PLL Bit of PLLCTL*/
*PLL1_PLLCTL |= 0x00000001; // PLLEN=0
GEL_TextOut("Turbo Mode:: PLL1:432Mhz enabled\n");
// GEL_TextOut("\n %dn",lock_status);
/****************PLL2 ********************************/
GEL_TextOut("Please wait PLL2 initialization is in Progress........\n");
/*Power up the PLL*/
*PLL2_PLLCTL &= 0xFFFFFFFD;
/*Disable the PLL*/
*PLL2_PLLCTL |= 0x10;
/*Bring the PLL out of Disable Mode*/
*PLL2_PLLCTL &= 0xFFFFFFEF;
/*Select the Clock Mode as Onchip Oscilator or External Clock on MXI pin*/
/*VDB has input on MXI pin */
*PLL2_PLLCTL &= 0xFFFFFEFF;
*PLL2_PLLCTL |= CLKSRC<<8;
/*Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR*/
*PLL2_PLLCTL &= 0xFFFFFFDF;
/*Set PLLEN=0 => PLL BYPASS MODE*/
*PLL2_PLLCTL &= 0xFFFFFFFE;
/*Wait at least 4 MXI clock or referene clock cycles to allow PLLEN mux switches properly to bypass clock*/
for(j=0; j<0x20; j++) {}
// PLLRST=1(reset assert)
*PLL2_PLLCTL |= 0x00000008;
for(j=0; j<0x100; j++) {} //added for testpurpose:uvj
/*Bring PLL out of Reset*/
*PLL2_PLLCTL &= 0xFFFFFFF7;
//Program the Multiper and Pre-Divider for PLL2
*PLL2_PLLM = 0x2D; // M=45 ; VCO will 24*2M/N+1 = 270Mhz
*PLL2_PREDIV = 0x8000|0x7; // N = 7
*PLL2_POSTDIV = 0x8000; // div by 1
*PLL2_SECCTL = 0x00470000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1
*PLL2_SECCTL = 0x00460000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0
*PLL2_SECCTL = 0x00400000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0
*PLL2_SECCTL = 0x00410000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1
// Post divider setting for PLL2
// *PLL2_PLLDIV1 = 0x8xxx; // POST DIV USB Alternate current setting will not yield 24Mhz use PLL1 AUXclk
*PLL2_PLLDIV2 = 0x8000; // POST DIV 270/1=270mhz -> ARM926/ARM968
// *PLL2_PLLDIV3 = 0x8xxx; // DDR 2X clk Alternate, used PLL1 for Turbo mode
*PLL2_PLLDIV4 = 0x8005; // POST DIV 270/6 ->VOICE, not necesarily divider, this needs to be computed properly
//*PLL2_PLLDIV5 = 0x800x; // POST DIV -> VENC for HD video cannot be used, external CLK must be used for VENC
*PLL2_PLLDIV5 = 0x8009; // POST DIV 270/10= 27Mhz -> VENC for SD video
//GoCmd for PostDivider to take effect
*PLL2_PLLCMD = 0x00000001;
/*Wait for PLL to LOCK */
while(! (((*PLLCFG1) & 0x07000000) == 0x07000000));
//Enable the PLL2
*PLL2_PLLCTL |= 0x00000001; // PLLEN=0
*PERI_CLKCTL &= 0xFFFFFFFB; //Enable CLKOUT2 driver
*PINMUX4 |= 0x300; //GIO31 will act as CLKOUT2
GEL_TextOut("Turbo Mode:: PLL2:270Mhz enabled\n");
}
//Setup & Initialize the DDR2 to work at 340Mhz
//-------------------------------------------
DDR16bitInit_340Mhz_test()
{
unsigned int j =0,PdNum=0;
//LPSC SyncReset DDR Clock Enable
*MDCTL_DDR = (((*MDCTL_DDR) & 0xffffffe0) | 0x00000001);
*PTCMD = (1<<PdNum);
while(! (((*PTSTAT >> PdNum) & 0x00000001) == 0));
while(!((*MDSTAT_DDR & 0x0000001F) == 0x1));
GEL_TextOut("DDR_EMIF Controller Sync Reset successful\n");
//LPSC DDR Clock Enable
*MDCTL_DDR = *MDCTL_DDR | 0x3;
*PTCMD = (1<<PdNum);
while(! (((*PTSTAT >> PdNum) & 0x00000001) == 0));
while(!((*MDSTAT_DDR & 0x0000001F) == 0x3));
//DLL & DataMacro Reset Assert
// *(DDR_PHY_VTP_IOCTRL) = *(DDR_PHY_VTP_IOCTRL) & 0xFFE7FFFF;
//Delay required for clocks to be stable
// for(j=0;j<100;j++)
// {
// }
//DLL & DataMacro Reset Deassert
// *(DDR_PHY_VTP_IOCTRL) = *(DDR_PHY_VTP_IOCTRL) | 0x00180000;
//Config Mode: DDR2
// Termination: Default
// ReadLatency: 0x4 (Will taken as 4+1 =5 DDR_CLKP cycles
// External DQS gatin enabled
*DDRPHYCTL1 = 0x000080C6;
*DDRPHYCTL2 = 0x00000000;
/*----------------------------DDR CFG----------------------------------------*/
//Program SDRAM Refresh Control Register
//Refresh Rate calculated for 340Mhz
//DifferentialDQS: Set
//DDR2,SDRAM :Enable
//Narrow Mode : Set -16bit DDR2
//CAS_latency :0x4
//Number of Banks:0x8
//PageSize :1024 words
//CE0 :Used
*SDCFG1 = 0x00D34A32;
*SDCFG1 = 0x0053CA32;
*SDTIM0 = 0x576D7D12;
*SDTIM1 = 0x422EC742;
*VBUSMP = 0x000000FE; //VBUSM Burst Priority Register, pr_old_count = 0xFE
*SDCFG1 = 0x08534832;
*SDREF = 0x00000541;
GEL_TextOut("DDR2 init is done for 16-bit Interface _340Mhz\n");
}
//Setup & Initialize the DDR2 to work at 270Mhz
//-------------------------------------------
DDR16bitInit_270Mhz_test()
{
unsigned int j =0,PdNum=0;
//LPSC SyncReset DDR Clock Enable
*MDCTL_DDR = (((*MDCTL_DDR) & 0xffffffe0) | 0x00000001);
*PTCMD = (1<<PdNum);
while(! (((*PTSTAT >> PdNum) & 0x00000001) == 0));
while(!((*MDSTAT_DDR & 0x0000001F) == 0x1));
GEL_TextOut("DDR_EMIF Controller Sync Reset successful\n");
//LPSC DDR Clock Enable
*MDCTL_DDR = *MDCTL_DDR | 0x3;
*PTCMD = (1<<PdNum);
while(! (((*PTSTAT >> PdNum) & 0x00000001) == 0));
while(!((*MDSTAT_DDR & 0x0000001F) == 0x3));
//DLL & DataMacro Reset Assert
// *(DDR_PHY_VTP_IOCTRL) = *(DDR_PHY_VTP_IOCTRL) & 0xFFE7FFFF;
//Delay required for clocks to be stable
// for(j=0;j<100;j++)
// {
// }
//DLL & DataMacro Reset Deassert
// *(DDR_PHY_VTP_IOCTRL) = *(DDR_PHY_VTP_IOCTRL) | 0x00180000;
//Config Mode: DDR2
// Termination: Default
// ReadLatency: 0x4 (Will taken as 4+1 =5 DDR_CLKP cycles
// External DQS gatin enabled
*DDRPHYCTL1 = 0x000080C6;
*DDRPHYCTL2 = 0x00000000;
/*----------------------------DDR CFG----------------------------------------*/
//Program SDRAM Refresh Control Register
//Refresh Rate calculated for 270Mhz
//DifferentialDQS: Set
//DDR2,SDRAM :Enable
//Narrow Mode : Set -16bit DDR2
//CAS_latency :0x4
//Number of Banks:0x8
//PageSize :1024 words
//CE0 :Used
*SDCFG1 = 0x00D34A32;
*SDCFG1 = 0x0053CA32;
*SDTIM0 = 0x45246412;
*SDTIM1 = 0x4225C742;
*VBUSMP = 0x000000FE; //VBUSM Burst Priority Register, pr_old_count = 0xFE
*SDCFG1 = 0x08534832;
*SDREF = 0x0000083A;
GEL_TextOut("DDR2 init is done for 16-bit Interface _270Mhz\n");
}
//Setup & Initialize the DDR2 to work at 216Mhz
//-------------------------------------------
DDR16bitInit_216Mhz_test()
{
unsigned int j =0,PdNum=0;
//LPSC SyncReset DDR Clock Enable
*MDCTL_DDR = (((*MDCTL_DDR) & 0xffffffe0) | 0x00000001);
*PTCMD = (1<<PdNum);
while(! (((*PTSTAT >> PdNum) & 0x00000001) == 0));
while(!((*MDSTAT_DDR & 0x0000001F) == 0x1));
GEL_TextOut("DDR_EMIF Controller Sync Reset successful\n");
//LPSC DDR Clock Enable
*MDCTL_DDR = *MDCTL_DDR | 0x3;
*PTCMD = (1<<PdNum);
while(! (((*PTSTAT >> PdNum) & 0x00000001) == 0));
while(!((*MDSTAT_DDR & 0x0000001F) == 0x3));
/*----------------------------DDR CFG----------------------------------------*/
//Program SDRAM Refresh Control Register
//Refresh Rate calculated for 216Mhz
//DifferentialDQS: Set
//DDR2,SDRAM :Enable
//Narrow Mode : Set -16bit DDR2
//CAS_latency :0x4
//Number of Banks:0x8
//PageSize :1024 words
//CE0 :Used
*DDRPHYCTL1 = 0x000080C5;
*DDRPHYCTL2 = 0x00000000;
/*----------------------------DDR CFG----------------------------------------*/
//Program SDRAM Refresh Control Register
//Refresh Rate calculated for 205Mhz
//This Values are for 216Mhz, but will run for slower Inputs
*DDRPHYCTL1 = 0x510064D4; //External DQS gatin enabled
*SDREF = 0x00000535; //Program SDRAM Refresh Control Register
*VBUSMP = 0x000000FE; //VBUSM Burst Priority Register, pr_old_count = 0xFE
*SDCFG1 = 0x0000C632; //Program SDRAM Bank Config Register
*SDTIM0 =0x2A923249; //Program SDRAM Timing Control Register1
*SDTIM1 =0x3c17C763; //Program SDRAM Timing Control Register2
*SDCFG1 = 0x00004632; //Program SDRAM Bank Config Register
*SDREF = 0x00000535; //Program SDRAM Refresh Control Register
GEL_TextOut("DDR2 init is done for 16-bit Interface _216Mhz\n");
}
hotmenu COLOR_BAR_PLL1()
{
/* SYSTEM Registers */
#define SYS_BASE 0x01C40000
#define SYS_VPSSCLK_CTRL *( unsigned int* )( SYS_BASE+0x44 )
#define SYS_VDAC_CONFIG *( unsigned int* )( SYS_BASE+0x2c )
/*VPSS DAC REGS*/
#define VPSS_BASE 0x01C70000
#define VPSS_VPBE_CLK_CTRL *( unsigned int* )( VPSS_BASE+0x200 )/* Changed for DM360 */
#define VPSS_VENC_VMOD *( unsigned int* )(VPSS_BASE+0x1e00)// (0x01C71e00)
#define VPSS_VENC_VIDCTL *( unsigned int* )(VPSS_BASE+0x1e04)// (0x01C71e04)
#define VPSS_VENC_VDPRO *( unsigned int* )(VPSS_BASE+0x1e08)//(0x01C71e08)
#define VPSS_VENC_DACTST *( unsigned int* )(VPSS_BASE+0x1ec4)//(0x01C71eC4)
#define VPSS_VPBE_CLKCTL *( unsigned int* )(VPSS_BASE+0x1f40)//(0x01C71e00+0x140)
#define VPSS_VENC_DACSEL *( unsigned int* )(VPSS_BASE+0x0F4)//
SYS_VPSSCLK_CTRL = 0x00000018; /*Drive venc clock with PLL1 output (divided down to 27MHz), enable VENC clock*/
VPSS_VPBE_CLK_CTRL = 0x01; //; /*Select enc_clk*1, turn on VPBE clk*/
SYS_VDAC_CONFIG = 0x081141CC; // take DACs out of power down mode
// Frame mode with no up-scaling
VPSS_VPBE_CLKCTL =0x11;// enable venc & digital LCD clock
GEL_TextOut( "VPSS Clock enabled\n" );
VPSS_VENC_VMOD =0x003;///* STD normal composite, Venc enabled*/
VPSS_VENC_VDPRO =0x300;// /*Enable 100% color bars*/
VPSS_VENC_DACTST =0x0;// (DACTST =0x0 was also tried and it did not work either)
VPSS_VENC_DACSEL =0x0;
GEL_TextOut("enable SD color bars\n");
}
hotmenu COLOR_BAR_PLL2()
{
/* SYSTEM Registers */
#define SYS_BASE 0x01C40000
#define SYS_VPSSCLK_CTRL *( unsigned int* )( SYS_BASE+0x44 )
#define SYS_VDAC_CONFIG *( unsigned int* )( SYS_BASE+0x2c )
/*VPSS DAC REGS*/
#define VPSS_BASE 0x01C70000
#define VPSS_VPBE_CLK_CTRL *( unsigned int* )( VPSS_BASE+0x200 )/* Changed for DM360 */
#define VPSS_VENC_VMOD *( unsigned int* )(VPSS_BASE+0x1e00)// (0x01C71e00)
#define VPSS_VENC_VIDCTL *( unsigned int* )(VPSS_BASE+0x1e04)// (0x01C71e04)
#define VPSS_VENC_VDPRO *( unsigned int* )(VPSS_BASE+0x1e08)//(0x01C71e08)
#define VPSS_VENC_DACTST *( unsigned int* )(VPSS_BASE+0x1ec4)//(0x01C71eC4)
#define VPSS_VPBE_CLKCTL *( unsigned int* )(VPSS_BASE+0x1f40)//(0x01C71e00+0x140)
#define VPSS_VENC_DACSEL *( unsigned int* )(VPSS_BASE+0x0F4)//
// SYS_VPSSCLK_CTRL = 0x00000018; /*Drive venc clock with PLL1 output (divided down to 27MHz), enable VENC clock*/
SYS_VPSSCLK_CTRL = 0x00000038; /*Drive venc clock with PLL2 output (divided down to 27MHz), enable VENC clock*/
VPSS_VPBE_CLK_CTRL = 0x01; //; /*Select enc_clk*1, turn on VPBE clk*/
SYS_VDAC_CONFIG = 0x081141CC; // take DACs out of power down mode
// Frame mode with no up-scaling
VPSS_VPBE_CLKCTL =0x11;// enable venc & digital LCD clock
GEL_TextOut( "VPSS Clock enabled\n" );
VPSS_VENC_VMOD =0x003;///* STD normal composite, Venc enabled*/
VPSS_VENC_VDPRO =0x300;// /*Enable 100% color bars*/
VPSS_VENC_DACTST =0x0;// (DACTST =0x0 was also tried and it did not work either)
VPSS_VENC_DACSEL =0x0;
GEL_TextOut("enable SD color bars\n");
}
hotmenu COLOR_BAR_PLL2_720pHD()
{
/* SYSTEM Registers */
#define SYS_BASE 0x01C40000
#define SYS_VPSSCLK_CTRL *( unsigned int* )( SYS_BASE+0x44 )
#define SYS_VDAC_CONFIG *( unsigned int* )( SYS_BASE+0x2c )
/*VPSS DAC REGS*/
#define VPSS_BASE 0x01C70200
#define VPSS_VPBE_CLK_CTRL *( unsigned int* )( VPSS_BASE+0x000 )/* Changed for DM360 */
#define VPSS_VENC_BASE 0x01C71E00
#define VPSS_VENC_VMOD *( unsigned int* )(VPSS_VENC_BASE+0x000)// (0x01C71e00)
#define VPSS_VENC_VIDCTL *( unsigned int* )(VPSS_VENC_BASE+0x004)// (0x01C71e04)
#define VPSS_VENC_VDPRO *( unsigned int* )(VPSS_VENC_BASE+0x008)//(0x01C71e08)
#define VPSS_VENC_DACTST *( unsigned int* )(VPSS_VENC_BASE+0x0c4)//(0x01C71eC4)
#define VPSS_VENC_CLKCTL *( unsigned int* )(VPSS_VENC_BASE+0x140)//(
#define VPSS_VENC_DACSEL *( unsigned int* )(VPSS_VENC_BASE+0x0F4)//
#define VPSS_VENC_XHINTVL *( unsigned int* )(VPSS_VENC_BASE+0x174)//
/*
* Setup clocking / DACs
*/
SYS_VDAC_CONFIG = 0x081141EF; // take DACs out of power down mode\
SYS_VPSSCLK_CTRL = 0x00000038; /*Drive venc clock with PLL2 output (divided down to 27MHz), enable VENC clock*/
// SYS_VPSSCLK_CTRL = 0x00000018; /*Drive venc clock with PLL1 output (divided down to 27MHz), enable VENC clock*/
VPSS_VPBE_CLK_CTRL = 0x00000011; //; /*Select enc_clk*1, turn on VPBE clk*
// Frame mode with no up-scaling
VPSS_VENC_CLKCTL =0x00000011;// enable venc & digital LCD clock
VPSS_VENC_XHINTVL = 0x00000000; // Extend standard 720P horizontal timing
GEL_TextOut( "VPSS Clock enabled\n" );
/*
* Setup VENC
*/
VPSS_VENC_VMOD =0x01c3;//1080i
VPSS_VENC_VDPRO =0x0100; // Colorbars not normal display mode
VPSS_VENC_DACTST =0x0000; // Power on DACs
VPSS_VENC_DACSEL =0x0543; // Component out on DACs
GEL_TextOut("enable HD color bars\n");
}
/* ------------------------------------------------------------------------ *
* *
* Setup_Pin_Mux( ) *
* Configure Pin Multiplexing *
* *
* ------------------------------------------------------------------------ */
//Setup_Pin_Mux( )
Setup_Pin_Mux( )
{
GEL_TextOut( "Setup PinMux... " );
*PINMUX0 = 0x00FD0000; // Video Yin, SD0, McBSP, SD1_CLK
*PINMUX1 = 0x00145555; // Video Cout, EXTCLK, FIELD
*PINMUX2 = 0x00000055; // EMIFA
*PINMUX3 = 0x375AFFFF; // SPI0, I2C, UART0, ENET, MDIO
*PINMUX4 = 0x55556555; // SD1, SPI1, SPI2, SPI4, USBDRVVBUS
GEL_TextOut( "[Done]\n" );
}
I2C_GPIO_pin_prime( )
{
#define GPIO_BASE ((unsigned int *)0x01C67000)
#define GPIO_DIR ((unsigned int *)0x01C67010)
#define GPIO_OUTPUT ((unsigned int *)0x01C67014)
int i; //define loop counter
int j;
/* Wiggle I2C clock line to make sure devices aren't hung */
*PINMUX3 &= 0xFF9FFFFF; // PINMUX for GIO20 instead of SCL
*GPIO_DIR &= 0xFFEFFFFF; //GIO20 SET AS (0-OUTPUT)
for (i = 0; i < 9; i++)
{
// EVMDM365_GPIO_setOutput(20, 0);
*GPIO_OUTPUT &= 0xFFEFFFFF; //GIO20 SET AS (0-LOW)
for (j = 0; j < 100; j++){
;// TIS IS FOR DELAY
}
*GPIO_OUTPUT |= 0x00100000; //GIO20 SET AS (0-HIGH)
}
*PINMUX3 |= 0x00400000; // Re-enable SCL
GEL_TextOut( "Setup GPIO20 Toggle ... \n " );
}
