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TMS320C6657: EDMA move problem

user5992872
Prodigy 140 points
Part Number: TMS320C6657
Other Parts Discussed in Thread: SYSBIOS

    I set up a project in the SYS / BIOS environment, which established a timer with a period of 100 microseconds and an EDMA triggered by GPINT2, using EDMA to move AD sampling data (sampling a sine wave signal), flip the GPIO2 signal to trigger GPINT2 signal in the timer interrupt, and then trigger the EDMA move, and store the sampled data in the EDMA transfer completion interrupt (stored in DDR, clear the value in the EDMA destination address after storage), that is, the timer (flip the GPIO signal)-EDMA transfer completion interrupt (storage)-timer cycle.

    However, during operation, it was found that using CCS to draw a waveform graph of the data in the storage area, there will be a case where the value in the storage area is 0 for a certain period of time (EDMA did not moved to the correct data), and then it returns to normal， normal data and data 0 alternately appears, but when this happens, the EDMA transfer completion interrupt will still be entered, and the transmission error signal will not be triggered, and the number of timer interrupts is the same as the number of EDMA transfer completion interrupts.

    This situation makes me very puzzled. The correct entry of the EDMA transfer completion interrupt indicates that EDMA believes that the data has been moved to, but why the data is 0 (the sampling data is not 0, the oscilloscope has been tested). then how should the problem be solved?

  • 0
    TI__Guru* 95265 points

    Hi,

    You stored the data in DDR3. There is no cache coherence between different masters (e.g, EDMA and CPU core), the software must maintain it. When you do an EDMA movement, the data should be in the DDR3 physical memory after the transfer completion. 

    I don't understand well "using CCS to draw a waveform graph of the data in the storage area", CCS view is the same as the DSP CPU view. DSP is still seeing the data in cache, not the same as in physical memory. You have to do a cache invalidate of L1D and L2 before using it. 

    Regards, Eric

  • 0 in reply to lding
    Prodigy 140 points

    Hello, cache is not enabled in my program. I first asked EDMA to fetch data from the memory area of EMIF to L1D or DDR (both of which will cause this problem), and store the data in the specified DDR area. This seems to have nothing to do with the caching of L1D and L2.

    Best wishes!

  • 0 in reply to user5992872
    TI__Guru* 95265 points

    Hi,

    How do you know that cache is not enabled? The SYSBIOS may enable L1D cache by default. Can you confirm from L1DCFG, L2CFG.L2MODE and MAR registers? Your test is timer interrupt =====>GPIO flip======> GPIO interrupt ======>EDMA event input ======>read over EMIF and put data into DDR3, correct? Can you confirm that number of timer interrupt matches the number of EDMA transfer completion interrupts? That is, EDMA always fired but sometimes you get 0 results?

    Without using the CCS to draw a figure and found 0, can you have a small code to check the each EDMA transfer if the data is 0 or not? If data is indeed zero, then I assume you can halt the core? Then look at the memory region use CCS memory browser with L1D and L2 boxes checked and unchecked to make sure the data is real zero?

    If data is really zero, please provide details about failure pattern, e.g., frequency of 0, length of 0, length of EDMA transfer, what is your EDMA OPT field programed? 

    Regards, Eric

  • 0 in reply to lding
    TI__Guru* 95265 points

    Any update?

    -Eric