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Compiler/TDA2PXEVM: Ethernet RGMII without MDIO --- connected to switch directly

Part Number: TDA2PXEVM


Tool/software: TI C/C++ Compiler

Dear all,

we got a customer board ,  it connected RGMII[0] to a switch(SJA1105P) port[5] , I did code modify as follows:

1.add 'pGMACSWConfig->macInitCfg[0].mdioModeFlags = MDIO_MODEFLG_NOPHY;' in file 'ndk_nsp_hooks,c' and set 'pGMACSWConfig->macInitCfg[i].macConnectionType =

MAC_CONNECTION_TYPE_RGMII_FORCE_100_FULL;'

2.disable MDIO in file 'network_ctrl_tsk.c' as shown as below 

"     

         status = Network_waitConnect(&pObj->sockObj, 1000);

MDIO_CtronlRegValueTemp = RD_MEM_32(0x48485004);
Vps_printf("network_ctrl_tsk.c line 272 MDIO_Control Reg : %X HAHAHAHHAHAH",MDIO_CtronlRegValueTemp);//read MDIO status
Vps_printf("network_ctrl_tsk.c line 273 CTRL_CORE_PAD_RGMII0_RXC Reg : %X HAHAHAHHAHAH",RD_MEM_32(0x4A003668));//read CTRL_CORE_PAD_RGMII0_RXC
Vps_printf("network_ctrl_tsk.c line 274 CTRL_CORE_PAD_RGMII0_TXC Reg: %X HAHAHAHHAHAH",RD_MEM_32(0x4A003650));//read CTRL_CORE_PAD_RGMII0_TXC
Vps_printf("network_ctrl_tsk.c line 274 CONFIG_REG_2 IODelay Reg: %X HAHAHAHHAHAH",RD_MEM_32(0x4844A014));//read IO delay
if(MDIO_CtronlRegValueTemp != (UInt32)0x00100000)
{
WR_MEM_32(0x48485004,0x00100000);
}

"

according to modification as above , I got data as follows:

"
[HOST ] 2083.594766 s: network_ctrl_tsk.c line 272 MDIO_Control Reg : 1100000 HAHAHAHHAHAH
[HOST ] 2083.594766 s: network_ctrl_tsk.c line 273 CTRL_CORE_PAD_RGMII0_RXC Reg : 40100 HAHAHAHHAHAH
[HOST ] 2083.594796 s: network_ctrl_tsk.c line 274 CTRL_CORE_PAD_RGMII0_TXC Reg: 100 HAHAHAHHAHAH
[HOST ] 2083.594796 s: network_ctrl_tsk.c line 274 CONFIG_REG_2 IODelay Reg: 5DE HAHAHAHHAHAH

"

After send arp package through CANOE I can't got response from TDA.

Is there anybody can help me to confirm those modifications are sufficient for TDA?

Thanks a lot.

 

  • Hello.

    To confirm, you are enabling MAC-to-MAC communication, starting with the NSP driver, correct?

    The MDIO flags and MAC connection type are correct for MAC-to-MAC.

    It’s not quite clear why only TXC, RXC and just one IOdelay register are printed in the shared code snippet. RGMII iodelay settings have to be done as per the data manual, i.e. for RGMII see section 5.10.6.18.3 of DM. Please do confirm that you are following the procedure outlined.

    Assuming this is correct, then we will want to check is if packets are being dropped in the GMAC. This can be checked in the GMAC STATS registers, see section 26.11.6.5 in TRM for details.

    Besure to check the STATS registers both before and after the CANOE test:
    • RX_CRC_ERRORS must be 0
    • RX_DMA_OVERRUNS must be 0
    • TX_UNDERRUN must be 0
    • GOOD_TX_FRAMES and GOOD_RX_FRAMES counter should have increased after the CANOE test

    Also, you may want to check if the RGMII internal delay is enabled in bits 25 or 26 of CTRL_CORE_SMA_SW_1 register (0x4A002534).

    Best regards,

    Dave

  • Hello Dave,

    Thanks for your  reply very much. All of your advices are very useful.

    1. I am not sure if it's MAC-to MAC with NSP, could you tell me how to confirm it?

    2.I did some test code to read register which I want to watch , as shows as below : 

    "

    Vps_printf("network_ctrl_tsk.c line 272 MDIO_Control Reg : %X HAHAHAHHAHAH",MDIO_CtronlRegValueTemp);//Lan
    Vps_printf("network_ctrl_tsk.c line 273 CTRL_CORE_PAD_RGMII0_RXC Reg : %X HAHAHAHHAHAH",RD_MEM_32(0x4A003668));//Lan
    Vps_printf("network_ctrl_tsk.c line 274 CTRL_CORE_PAD_RGMII0_TXC Reg: %X HAHAHAHHAHAH",RD_MEM_32(0x4A003650));//Lan
    Vps_printf("network_ctrl_tsk.c line 275 CONFIG_REG_2 IODelay Reg: %X HAHAHAHHAHAH",RD_MEM_32(0x4844A014));//Lan
    Vps_printf("network_ctrl_tsk.c line 276 RX_CRC_ERRORS Reg: %X HAHAHAHHAHAH",RD_MEM_32(0x48484910));
    Vps_printf("network_ctrl_tsk.c line 277 RX_DMA_OVERRUNS Reg: %X HAHAHAHHAHAH",RD_MEM_32(0x4848498C));
    Vps_printf("network_ctrl_tsk.c line 278 TX_UNDERRUN Reg: %X HAHAHAHHAHAH",RD_MEM_32(0x4848495C));
    Vps_printf("network_ctrl_tsk.c line 279 GOOD_TX_FRAMES Reg: %X HAHAHAHHAHAH",RD_MEM_32(0x48484934));
    Vps_printf("network_ctrl_tsk.c line 280 GOOD_RX_FRAMES Reg: %X HAHAHAHHAHAH",RD_MEM_32(0x48484900));
    Vps_printf("network_ctrl_tsk.c line 281 CTRL_CORE_SMA_SW_1 Reg: %X HAHAHAHHAHAH",RD_MEM_32(0x4A002534));

    "

    3.I got those register's data  as shown as below:

    "


    [HOST ] 200.166290 s: network_ctrl_tsk.c line 272 MDIO_Control Reg : 1100000 HAHAHAHHAHAH
    [HOST ] 200.166290 s: network_ctrl_tsk.c line 273 CTRL_CORE_PAD_RGMII0_RXC Reg : 40100 HAHAHAHHAHAH
    [HOST ] 200.166320 s: network_ctrl_tsk.c line 274 CTRL_CORE_PAD_RGMII0_TXC Reg: 100 HAHAHAHHAHAH
    [HOST ] 200.166320 s: network_ctrl_tsk.c line 275 CONFIG_REG_2 IODelay Reg: 5DE HAHAHAHHAHAH
    [HOST ] 200.166320 s: network_ctrl_tsk.c line 276 RX_CRC_ERRORS Reg: 0 HAHAHAHHAHAH
    [HOST ] 200.166320 s: network_ctrl_tsk.c line 277 RX_DMA_OVERRUNS Reg: 0 HAHAHAHHAHAH
    [HOST ] 200.166320 s: network_ctrl_tsk.c line 278 TX_UNDERRUN Reg: 0 HAHAHAHHAHAH
    [HOST ] 200.166351 s: network_ctrl_tsk.c line 279 GOOD_TX_FRAMES Reg: 0 HAHAHAHHAHAH
    [HOST ] 200.166351 s: network_ctrl_tsk.c line 279 GOOD_RX_FRAMES Reg: 28 HAHAHAHHAHAH
    [HOST ] 200.166351 s: network_ctrl_tsk.c line 279 CTRL_CORE_SMA_SW_1 Reg: 0 HAHAHAHHAHAH

    "

    the 'GOOD_RX_FRAMES' increase every time while running CANOE test, Should I think those configuration are OK?

    I have tried to set CPSW_CONTROL as "FIFO_LOOPBACK" then I can watch echo data in CANOE. is it means driver configuration right?

    Thanks for your help.

    Best regards,

    Lan

  • Lan,

    For #1 I was confirming that your original information looks correct for this configuration, and asking intent. I think this is fine.

    For #2, I see from CTRL_CORE_SMA_SW_1 == 0 that the internal delay is enabled. Thanks for confirming this.

    GOOD_RX_FRAMES increasing during test should mean this configuration is good. Once you enable loopback you'll hopefully see the TX as well.

    Best regards,

    Dave