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How to retransmit an Ethernet packet

Tom Lin
Prodigy 30 points

We are using DM642 DSP EMAC to send/receive Ethernet packets and have the following questions about the functionality of EMAC Tx control :

1) After all the packets in Tx channels are transmitted, will the Tx stop automatically? If it does, how do I restart the EMAC Tx Controller? If it does not, how do I stop the Tx?

2) As I understand, both CPU and EMAC can update the EMAC internal memory at the same time, which can cause race condition. Is there a way to lock the internal memory temporarily so CPU can update the descriptor list safely?

3) In the middle of packet transmission, if there is Tx error such as Tx Underrun, how do I retransmit this packet so the transmission sequence will not be out of order?

  • 0
    TI__Expert 5750 points

    Hello,

    1) After transmit of the TX channels complete, TX will still stay enabled and re-start once the TxnHDP is updated.

    Are you using NDK ? http://focus.ti.com/docs/toolsw/folders/print/ndktcpip.html

    Regards

    Varada

  • 0 in reply to Varada Bellary
    Prodigy 30 points

    Dear Varada,

    Thanks for the information.

    We do not use NDK in order to save memory space and to use EMAC hardware directly for high speed switching.

    Wonder if EMAC resets TxnHDP to 0 or not when it finish the packet transmission?

    Is there any condition that could disable or temporarily suspend EMAC TX?

    Best regards,

    Tom Lin

    V2 Technology Inc.

  • 0 in reply to Tom Lin
    TI__Expert 5750 points

    Q : Does EMAC reset TxHDP , after TX is done ?

    A : I believe No. It will only update the Intt Acknowledge register.

     

    Q. Is there any condition that could disable or temporarily suspend EMAC TX?

    A.  Not when the entire descriptor has not finished. Was the next pointer updated after the TxnHDP was written ?

     

     About the potential race condition, can you refer to the software suggestion mentioned in 2.3.2, about processing of the TX/RX descriptor queues.

    http://focus.ti.com/lit/ug/spru628a/spru628a.pdf

     

    Hope this helps.

    Regards

    Varada

     

  • 0 in reply to Varada Bellary
    Prodigy 30 points

    Thanks for the tip.

     

    I have read through spru628a.pdf and we follow the rules using 2 TX channels for packet transmission. The transmission seems working OK for light traffics. When we generated high volume of data traffic, EMAC got malfunctioned in a couple minutes (can be reproduced): EMAC TX/RX stopped and all EMAC registers were set to 0. This condition couldn't be corrected by software and had to be restart by hardware reset. When DSP is in this condition, only EMAC has problem, all other peripherals seems working OK. Wonder if there is a quick answer for what could cause such result? Such as certain register must not be accessed in certain occasions or others.

     

    Very appreciate,

     

    Tom

  • 0 in reply to Tom Lin
    TI__Expert 5750 points

    This may point to a race condition.

    Are there any error conditions that get set, or the HOSTPEND interrupt set?

    Also - Can you cycle through more TX channels, instead of 2 fixed TX channels ?

    Also please provide more details about how your driver processes the interrupts.

    For reference - you can see the source code of NDK 2.0.

    http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ndk/index.html

    Thanks

    Varada