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AM4376: NOR boot issue

Part Number: AM4376


Please note that I can share details of this problem, including board schematic, through private channels. I would greatly appreciate a direct contact to help resolve this.

We are in the midst of transitioning one of our avionics PCBAs from an AM335x to the AM4376. We are attempting to boot off a S29GL01GS10DHI010 parallel ROM. We have hit multiple issues here, and I am currently trying to understand the TRM rev I statement (section 5.2.8.2, page 238): "The be1n pin on the flash device needs to be connected to gpmc_csn2." Does this apply to the given part number, which has no byte enables? Is there a reference implementation or qualified part list for parallel NOR with the AM4x?

https://e2e.ti.com/support/processors/f/791/t/468490?AM437x-Asynchronous-Parallel-NOR-Flash-Interface-Booting suggests that this should be possible...

We are blocked in our avionics migration until this issue is resolved. Would greatly appreciate follow-up with guidance on how to debug/procede.

  • Adam, the part you reference is a NAND flash (block based access) rather than a NOR flash, so section 5.2.8 doesn't apply.  NAND boot is described in 5.2.6.4.  

    What is your boot sequence?  Assuming you have JTAG access, can you confirm your boot sequence by reading CONTROL_STS register (0x44E10040).  When the board boots, can you probe the signals to the memory.  At this point, we are just looking for proper voltage levels and toggles on expected signals (CS, control and data)

    Regards,

    James

  • I think we might be using different definitions here, but both the manufacturer (Spansion/Cypress) and our reseller of that part consider it NOR; while it does use page-based writes, it's direct random-access for reads; and I'd imagine the bootloader only reads. (Just explaining my confusion here -- if this part needs to be configured for NAND-mode booting, we can go from there; I'd just like to understand how we got this confused!) Can you give an example of a part number that would be NOR and meet the part's parallel-NOR-booting requirements?

    We do have JTAG, but (a) we're unable to set a breakpoint immediately after start, even though this works fine on the AM3x, so our boot-time visibility is limited (this is another pain point that we'd love to understand/address), and (b) the BGA package for both the flash and the µP make probing memory signals hard. Is there any chance we can take this to e-mail so I can disclose a bit more about what we can measure, give you info about what we're seeing in detail, etc?

  • Ok, sorry, i did not look into the datasheet enough.  Yes, this is a parallel NOR flash.  I sent you a request to take this offline.

    Regards,

    James