AM3352: VTP register configuration for low power modes

Hi,

Now I reference to this file:https://processors.wiki.ti.com/index.php/AM335x_StarterWare_Power_management#DDR_Self-Refresh to implement power management.I use AM3352 in my project.

In this file,it has the following steps to configure DDR to low power state:

Configure DDR for low power

1. Configure DDR I/O for weak pull down.
2. Configure DDR to Dynamic Power Down.
3. Disable VTP.
4. Enable SRAM LDO Ret Mode.

I reference to the source code:ti\AM335X_StarterWare_02_00_00_01\examples\evmAM335x\demo\slpWkup_cgttms470.asm,the related code to disable VTP is:

;/* Disable VTP with N & P = 0x1 */
ldr r1, virt_ddr_vtp_ctrl
ldr r2, susp_vtp_ctrl_val
str r2, [r1]

virt_ddr_vtp_ctrl:
.word 0x44E10E0C
susp_vtp_ctrl_val:
.word 0x10117

After I set this register,I use this filr:https://git.ti.com/cgit/sitara-dss-files/am335x-dss-files/plain/am335x-ddr-analysis.dss?h=master to check the registers value,the nanlysis result said:

CONTROL：VTP_CTRL=0x00010117

     *VTP not disabled (expected in normal operation,but not DS0)

So how can I do to set the VTP register correctly?

Also,I have another question,to put DDR into self refresh mode,the source code is:

; Putting DDR into self refresh mode
LDR r0, _EMIF_PMCTL
LDR r1, [r0, #0]
ORR r1, r1, #0xA0
STR r1, [r0, #0]

_EMIF_PMCTL:
.word 0x4C000038

Except this code,do I need to do extra work to put DDR into self refresh mode?

"ORR r1, r1, #0xA0",is the value:0xA0 should I have to change?

DDR2 is used in my project.

Thank you!