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Original question:

TMS320C6742: Serial Flashing Host Utility sfh_OMAP-L138 usage for C6742 DSP

TMS320C6748: EMIFA NAND Configuration via GEL file

David Rivera
Prodigy 120 points
Part Number: TMS320C6748

Hi,

We are trying to flash our binary in NAND for LCDK TMS320C6748 using the NAND Writer CCS project. We have done it previously with SFH application successfully.

With that purpose I managed to import the legacy CCSv3.3 NANDWriter_DSP project following the doc with instructions I found in this thread:

https://e2e.ti.com/support/processors/f/791/t/665109?TMS320C6748-Serial-Flash-Loading-Utility-for-OMAP-L138-hanging-when-programming-an-8-bit-bus-NAND-Flash-chip

and solving some additional warnings by myself.

To set up for the LCDK TMS320C6748 I assume just the following settings need to be done:

- Set up the debugger configuration via a suitable .ccxml file

- Change NAND buswith to 16 bits in nandwriter.c, line 81

- Include a suitable GEL file to configure the PLLs, memory interfaces, etc, accordingly

Could you please confirm there are no additional settings I could be missing?

My real question is related to the last point, the GEL file. I have taken the sample GEL file "C6748_LCDK.gel" you provide within the StarterWare Tools. We have tested the DDR initialization routine with other tests we have performed, so we know it works. Nevertheless, I have some doubts regarding NAND initialization. The routine defined in the GEL file is the following (from line 547):

hotmenu EMIFA_NAND_PINMUX() {
PSC0_LPSC_enable(0, LPSC_EMIFA);
PINMUX7 = (PINMUX7 & ~0x00FF0FF0) | 0x00110110;
PINMUX8 = 0x11111111;
PINMUX9 = 0x11111111;
PINMUX12 = (PINMUX12 & ~0x0FF00000) | 0x01100000;
EMIFA_ACFG3 |= 0x1;
EMIFA_NANDFCR = (EMIFA_NANDFCR & ~0x30) | 0x12;

GEL_TextOut("\tEMIFA Pins Configured for NAND.\n","Output",1,1,1);
GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

I have some doubts for:

PINMUX7: My guess would be instead 0x10110010, which means two differences:

- Configures also EMA_WAIT[0] pin (PINMUX7 bits 31-28), which appears to be connected to the NAND device regarding the pinout description in the LCDK schematics.

- Do not configure CS4 (PINMUX7 bits 11-8), which seems completely unnecessary.

EMIFA_ACFG3: It just sets the bit 0, whereas the common .cfg files I have seen in some threads define a value of 0x3FFFFFFD to establish loose timing constraints among other settings, including also setting bit 0 related to the 16-bit buswidth. Is there any reason for that? I would go for 0x3FFFFFFD, would that be correct?

Thanks in advance,

David

  • 0
    Prodigy 120 points

    Today we managed to make it work, with the values I posted for the registers PINMUX7 and EMIFA_ACFG3. I wonder why a file that is supposed to work "out of the box" for a development kit does not have the correct settings (for EMIFA_ACFG3 probably it does not matter, but PINMUX7 was certainly wrong). 

    Also, the DEVICE_init routine in nandwriter.c line 118 is completely redundant to the PLL, PSC, DDR settings done in the GEL file (except for the KICK unlock routines which, as it is explained in the code itself, have no effect in recent silicon versions). I commented it to allow the GEL file do the work. If you are editting the GEL settings that could cause a conflict.

    With all respect, I think TI should make an effort here to set these flashing tools up to date. The documentation is scarce and sadly mainly based on people fighting the same problems with slight differences over and over again.

    Best regards,

    David