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PROCESSOR-SDK-DRA8X-TDA4X: does tda4x support OSPI boot with DDR x8 mode (D0~D7)?

chj yang
Prodigy 200 points

Part Number: PROCESSOR-SDK-DRA8X-TDA4X

hi , TI team:

in my custom board, I am using TDA4's OSPI interface to connect to a Micron OSPI flash which boot in DDR x8 mode (D0~D7).

my sdk version is psdk_rtos_auto_j7_06_01_00_15. I have two questions about the OSPI , as follow:

1、Does TDA4X support OSPI boot with DDR x8 mode?

2、OSPI of TDA4 EVM board works in SDR x1 mode(D0 input, D1 output) after power on. Does the Linux kernel supports OSPI driver with working in DDR x8 mode after power on?

  • 0
    TI__Guru* 77804 points

    Hi,

    chj yang said:
    Does TDA4X support OSPI boot with DDR x8 mode?

    Yes we support booting from OSPI in x8 mode. The OSPI SBL can be used for booting. It configures the OSPI for 133MHz DDR mode. Source for the OSPI SBL can be found in pdk/packages/ti/boot/sbl/src/ospi/.

    EDIT: ROM does not support x8 boot mode. Flash has to be in x1 mode. ROM uses 1S-1S-8S mode to be exact. Flash has to be handed over to kernel in x1 mode. Kernel will then reconfigure flash to x8 mode after parsing SFDP and other static data. Apologies for the miscommunication earlier.

    chj yang said:
    OSPI of TDA4 EVM board works in SDR x1 mode(D0 input, D1 output) after power on. Does the Linux kernel supports OSPI driver with working in DDR x8 mode after power on?

    Yes the linux kernel supports OSPI driver in DDR x8 mode.

    EDIT: Kernel/U-Boot does not support booting in x8 mode. Flash has to be handed over to kernel in x1 mode. Kernel will then reconfigure flash to x8 mode after parsing SFDP and other static data.
    This is because ROM does not support x8 boot on TDA4 (ROM uses 1-1-8 mode and flash needs to be in x1 mode for ROM to detect flash).
    There is a plan to add supporting for booting in x8 mode once ROM support xSPI boot in upcoming devices.

    Regards,

    Karan

  • 0 in reply to Karan Saxena
    Prodigy 200 points

    Hi，Karan:

         Thanks for your reply.

          My custom flash boot in DDR X8 mode, so I modified the linux driver. Now I can correctly read the flash ID of 6 bytes in DDR x8 mode , but I can‘t read the correct SFDP value. In the Linux kernel, the OSPI driver reads 16 bytes of SFDP in DAC mode as 0x53 0x46 0x44 0x50 0x6 0x1 0xff 0x53 0x46 0x44 0x50 0x6 0x1 0xff，and the correct value should be 0x53 0x46 0x44 0x50 0x6 0x1 0xff 0x00 0x06 0x01 0x10 0x30 0x00 0xff. It looks like the last 8 bytes are the same as the first 8 bytes. What is the cause of this error?

    Regards,

    chj

  • 0 in reply to chj yang
    TI__Guru* 77804 points

    Hi Chj,

    In my earlier reply I've added the EDIT. I checked with the experts and seems like there was some miscommunication at my end.

    Please let me know if after reading that, you have more questions.

    Regards,

    Karan

  • 0 in reply to Karan Saxena
    Prodigy 200 points

    Hi, Karan:

         thanks very much for your update.

       1、ROM uses 1S-1S-8S mode to be exact. is DDR or SDR?

       2、The following table shows the baud rate calculation in OSPI_CONFIG_REG register. The "master reference clock" in the table is the "assigned-clock-rates = <133333333>" field in the DTS. Although bits 19-22 are set to 0, the output clock of OSPI is "master reference clock" / 2 = 66. 6M， so if I want the OSPI output clock to be 133m, do I need to change the "assigned-clock-rates" field in DTS to 266M?

    Regards,

    chj

  • 0 in reply to chj yang
    Prodigy 200 points

    hi，TI team:

          Are there any new ideas on these two questions? Or do I need to restart another thread ?

    Regards,

    chj

  • 0 in reply to chj yang
    TI__Guru* 77804 points

    Hi Chj,

    chj yang said:
    ROM uses 1S-1S-8S mode to be exact. is DDR or SDR?

    This is SDR, "s" denotes the SDR here.

    chj yang said:
    The following table shows the baud rate calculation in OSPI_CONFIG_REG register. The "master reference clock" in the table is the "assigned-clock-rates = <133333333>" field in the DTS. Although bits 19-22 are set to 0, the output clock of OSPI is "master reference clock" / 2 = 66. 6M， so if I want the OSPI output clock to be 133m, do I need to change the "assigned-clock-rates" field in DTS to 266M?

    Can you please refer - https://e2e.ti.com/support/processors/f/791/p/910115/3378252#3378252 and see if this answers your question.

    Regards,

    Karan