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AM3358: DDR3 routing specification

Bart
Expert 6460 points
Part Number: AM3358

Hi,

We are having some problems with DDR3 and AM3358, where segmentation faults or freezing can occur. Changing the DDR clock from 400MHZ to 303MHz doesn't help. We found out that the Sitara's clock changed to 800MHz from 1GHz stabilizes this, tough it's dfficult to find any error within Addr/Cmd or in the Data lines.

Looking into potential issues in routing, we found out in the BeagleBone Black design that the length of the vias are not calculated into the DDR data trace length (should be important if the PCB thickness are 1.5 mm and the trace was routed on the bottom side of the PCB.)

For example on the BBB design the DDR_D15 is routed on the top and DDR_D10 is routed on the bottom. They are length matched without lengths of the two vias on the DDR_D10. The AM3358 Datasheet, Rev.L, Section 7.7.2.3.6.1 CK and ADDR_CTRL Routing Specifiication (Page 186) states that "extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8".

  • Does the extra 300 mills apply also to the data line as well?

Thank you.

  • 0
    TI__Guru* 87040 points

    Bart,

    Ideally the routing of the data signals should stay on one layer, or if you need to add vias, ideally all signals in the byte should have the same number of vias. 

    Unless you specifically violated the routing guidelines, there should be enough margin in your design.  A few questions:

    -what is is topology of your design?

    -did you follow the configuration outlined in this appnote:  https://www.ti.com/lit/pdf/sprack4  This provides a spreadsheet to calculate proper delay ratios for proper configuration of the EMIF controller and PHY.  Note if you have a point-to-point design, you don't need to run the software leveling routine, the spreadsheet will give you optimal values

    -if you post you DDR part number and spreadsheet, i can check it for correctness.  

    Regards,

    James

  • 0 in reply to JJD
    TI__Expert 6460 points

    Hi James,

    The topology and the schematic are still the same (you helped us some time ago on this) - I will share with you the details offline.

    Since that time, the build up was adapted to reach lower impedance and the routing of the DDR on the PCB was also changed.

    Yes, the app note was followed, but got different values than from the RatioSeed_AM335x_boards_V3 spreadsheet. Could not change the CMDx_REG_PHY_INVERT_CLKOUT_0 to 0 at Step3-Board Details in the AM335x_EMIF_Configuration_Tool_v3_EP+CPU-REV3 spreadsheet.

    As for DDR memory, it is MT41K256M16TW-107 XIT:P from Micron. As second option, IS43TR16256BL-107MBLI from ISSI will be used.

    Thanks for your feedback.

  • 0 in reply to Bart
    TI__Guru* 87040 points

    Bart, please use the values from the latest spreadsheet on the web.  I double checked the spreadsheet you sent and everything looks good.  This spreadsheet was updated from the previous spreadsheets and includes optimizations for better DDR configuration, one of which includes the INVERT_CLKOUT=1.   

    The new spreadsheet also includes GEL and u-boot tabs to use directly in your code.  Check the app note on how to apply these to your code.

    Regards,

    James 

  • 0 in reply to JJD
    TI__Expert 6460 points

    Hi James,

    We updated the different values from the AM335x_EMIF_Configuration_Tool_v3_EP+CPU-REV3 spreadsheet and made some test with test-memory.sh, and we got the same failure as before (I've attached in 90.1_problem.txt file):

    Fullscreen 90.1.problem.txt Download 
    Unable to handle kernel paging request at virtual address b497a000
Unable to handle kernel paging request at virtual address 003cd520
pgd = c0004000
[003cd520] *pgd=00000000
Internal error: Oops: 5 [#1] PREEMPT ARM
CPU: 0 PID: 63 Comm: irq/45-4a100000 Not tainted 4.14.71-rt44-eppfl1-g3b14af41729c #1
Hardware name: Generic AM33XX (Flattened Device Tree)
task: de24e580 task.stack: de44a000
PC is at dma_cache_maint_page+0x58/0x128
LR is at __dma_page_dev_to_cpu+0x80/0x120
pc : [<c0114430>]    lr : [<c01146d0>]    psr: 600f0113
sp : de44bd30  ip : de44bd68  fp : de44bd64
r10: 003cd520  r9 : 00000002  r8 : c0908300
r7 : de673240  r6 : 010c6e29  r5 : 000005fe  r4 : 00000742
r3 : c09ba758  r2 : 01046e29  r1 : dfaf1000  r0 : 208dc520
Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment none
Control: 10c5387d  Table: 9d158019  DAC: 00000051
Process irq/45-4a100000 (pid: 63, stack limit = 0xde44a210)
Stack: (0xde44bd30 to 0xde44c000)
bd20:                                     00000000 c09ba758 de44bd54 000005fe
bd40: 00000742 003cd520 de673240 00000002 00010000 c011524c de44bd94 de44bd68
bd60: c01146d0 c01143e4 c0118914 c0377568 c09c24c4 e00defc0 de3d59d0 de434f90
bd80: de673240 00000082 de44bda4 de44bd98 c011529c c011465c de44bddc de44bda8
bda0: c04afda0 c0115258 00000000 c05e43c0 00000000 de3d59d0 00010000 de3d59f0
bdc0: 00000082 e00defc0 de434f90 4a102fc0 de44be14 de44bde0 c04aff30 c04afd1c
bde0: c016c614 e00de000 de1f6800 00000000 de3d59d0 00000040 de403638 00000040
be00: 00000040 00000000 de44be34 de44be18 c04b1030 c04afddc de403638 00000000
be20: 00000001 de403638 de44be5c de44be38 c04b2fa8 c04b1000 de403638 c097bd80
be40: c097bd80 00000001 c091cab8 00000040 de44becc de44be60 c05334f4 c04b2f08
be60: c0929900 ffffcc90 c09062c4 0000012c de44be70 de44be70 de44be78 de44be78
be80: de44be80 de44be80 00000000 00000001 00000008 c091cab8 00000003 c05e4140
bea0: 00000003 00000003 0000000c c098cd40 ffffe000 c091cab8 c097c1ec 00000000
bec0: de44bf14 de44bed0 c01324ec c0533320 de44bef4 de44bee0 c0132e50 00000060
bee0: c098cd4c 00208040 de44bf0c de436680 de1f6800 00000001 c0169c3c ffffe000
bf00: 00000001 de436758 de44bf24 de44bf18 c0132d04 c0132304 de44bf44 de44bf28
bf20: c0169c98 c0132ca4 de1f6800 de436680 ffffe000 c0169c3c de44bf74 de44bf48
bf40: c0169edc c0169c48 00000000 c0169ce8 de436740 de4366c0 ffffe000 de0efb94
bf60: de436680 c0169dac de44bfac de44bf78 c014a9fc c0169db8 00000000 00000000
bf80: de44bfac de4366c0 c014a8d0 00000000 00000000 00000000 00000000 00000000
bfa0: 00000000 de44bfb0 c0107dd0 c014a8dc 00000000 00000000 00000000 00000000
bfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
bfe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
[<c0114430>] (dma_cache_maint_page) from [<c01146d0>] (__dma_page_dev_to_cpu+0x80/0x120)
[<c01146d0>] (__dma_page_dev_to_cpu) from [<c011529c>] (arm_dma_unmap_page+0x50/0x5c)
[<c011529c>] (arm_dma_unmap_page) from [<c04afda0>] (__cpdma_chan_free+0x90/0xc0)
[<c04afda0>] (__cpdma_chan_free) from [<c04aff30>] (__cpdma_chan_process+0x160/0x16c)
[<c04aff30>] (__cpdma_chan_process) from [<c04b1030>] (cpdma_chan_process+0x3c/0x58)
[<c04b1030>] (cpdma_chan_process) from [<c04b2fa8>] (cpsw_rx_poll+0xac/0xc4)
[<c04b2fa8>] (cpsw_rx_poll) from [<c05334f4>] (net_rx_action+0x1e0/0x484)
[<c05334f4>] (net_rx_action) from [<c01324ec>] (do_current_softirqs+0x1f4/0x39c)
[<c01324ec>] (do_current_softirqs) from [<c0132d04>] (__local_bh_enable+0x6c/0xa4)
[<c0132d04>] (__local_bh_enable) from [<c0169c98>] (irq_forced_thread_fn+0x5c/0x60)
[<c0169c98>] (irq_forced_thread_fn) from [<c0169edc>] (irq_thread+0x130/0x208)
[<c0169edc>] (irq_thread) from [<c014a9fc>] (kthread+0x12c/0x144)
[<c014a9fc>] (kthread) from [<c0107dd0>] (ret_from_fork+0x14/0x24)
Code: e5982000 e5931000 e0462002 e081a282 (e7912282)
---[ end trace 0000000000000002 ]---
genirq: exiting task "irq/45-4a100000" (63) is an active IRQ thread (irq 45)
pgd = dd158000
[b497a000] *pgd=00000000
Internal error: Oops: 805 [#2] PREEMPT ARM
CPU: 0 PID: 760 Comm: sport Tainted: G      D         4.14.71-rt44-eppfl1-g3b14af41729c #1
Hardware name: Generic AM33XX (Flattened Device Tree)
task: de70e580 task.stack: dd0e2000
PC is at __memzero+0x24/0x7c
LR is at 0x0
pc : [<c05cb044>]    lr : [<00000000>]    psr: 200f0113
sp : dd0e3b04  ip : 00000000  fp : dd0e3b6c
r10: 00000001  r9 : 00000200  r8 : b497a000
r7 : 00000001  r6 : dfe92f40  r5 : 00000000  r4 : c0979798
r3 : 00000000  r2 : 00000000  r1 : 00000fc0  r0 : b497a000
Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment none
Control: 10c5387d  Table: 9d158019  DAC: 00000051
Process sport (pid: 760, stack limit = 0xdd0e2210)
Stack: (0xdd0e3b04 to 0xdd0e4000)
3b00:          c01e1aa4 ddc84abc c02057e8 de7508bc c077561c dd0e3b34 dfac08fc
3b20: 00000000 00000000 00000000 014080c2 00000001 c097a0ec 00000000 dd0e3bc8
3b40: dfe83480 c0905d54 00000000 00000001 00000000 de70e580 00000000 de4ccc00
3b60: dd0e3c2c dd0e3b70 c01e2190 c01e117c 00000000 dfe83500 dd0e3bc4 dfe83480
3b80: dd0e3bd8 00000000 c097cc8c c05e43c0 00000000 00000000 dd0e3bbc dd0e3ba8
3ba0: c05e43c0 c01e17b0 c0979798 00000000 dd0e3c24 dd0e3bc0 c01e17b0 014080c2
3bc0: 00000000 c0159110 c097a0ec 00000000 c097a0ec 00000000 00000001 00000000
3be0: c098e290 c01594a0 de70e580 c0923da8 600f0193 00000000 dd0e3c14 dd0e3c08
3c00: c0377550 dd158008 dd158008 de4ccc00 00000000 de70e580 00000005 de4ccc00
3c20: dd0e3c5c dd0e3c30 c0208254 c01e20d8 00000000 dd158008 de7246c0 00000014
3c40: 00000000 de70e580 00000005 de4ccc00 dd0e3cd4 dd0e3c60 c020af2c c0208230
3c60: ffffe000 de07bf00 dd0e3c84 dd0e3c78 de7246c0 00000014 014000c0 000003c7
3c80: 003c7000 dd158008 dd158008 00000000 00000000 00000000 00000000 00000000
3ca0: 00000000 00000000 dd0e3cd4 dd0e3df8 003c7b20 de7246c0 00000014 de70e580
3cc0: 00000005 de4ccc00 dd0e3d2c dd0e3cd8 c0113b30 c020ad1c dd0e3d04 00002000
3ce0: de07bf00 c016964c de07bf00 00000002 dd0e3d14 00000000 00000000 de4ccc4c
3d00: 00000000 00000005 003c7b20 00000005 dd0e3df8 c0908300 dd0e2000 003c7b20
3d20: dd0e3d4c dd0e3d30 c0113dbc c01139b8 00000005 003c7b20 c090aa9c dd0e3df8
3d40: dd0e3df4 dd0e3d50 c0101254 c0113d9c ffffffff c014c204 dd0e3d8c dd0e3d68
3d60: c014c204 c010f54c c0909f98 00000002 de254000 c014c2fc 00000000 00000002
3d80: dd0e3db4 c0152468 dd0e3dcc c01572f8 de70e5b0 c0923da8 81e0348a 00000003
3da0: 00000009 de70e934 dd0e3dec dd0e3db8 c01572f8 c0157138 dd0e3e50 c092b94c
3dc0: 00003430 00000000 de70e580 de70e580 c0923da8 c014c204 c0114430 a00f0013
3de0: ffffffff dd0e3e2c dd0e3e7c dd0e3df8 c010d3b8 c0101218 003c7b20 00000000
3e00: 0001e3d9 c09ba758 00000210 00000114 0009e3d9 003c7b20 c0908300 00000001
3e20: 003c7b20 dd0e3e7c dd0e3e80 dd0e3e48 c0114534 c0114430 a00f0013 ffffffff
3e40: 00000051 bf000000 dd0e3eac c09ba758 c05e0528 00000210 00000114 00000001
3e60: 003c7b20 c09c6718 dd0e2000 00000000 dd0e3ea4 dd0e3e80 c0114534 c01143e4
3e80: c0118904 c05e4140 de3e6c10 c0114588 de200a10 c0981520 dd0e3eb4 dd0e3ea8
3ea0: c01145d0 c011450c dd0e3f0c dd0e3eb8 c045a814 c0114594 dd0e3f1c dd0e3ec8
3ec0: c05e33d4 c017e9c4 0000c350 00000000 00000001 00000000 dd0e3f20 00000001
3ee0: de70e580 c05e447c 00000114 00000114 c09c60a8 00000000 c09c685c 00000000
3f00: dd0e3f34 dd0e3f10 c045ac9c c045a6a4 c022cadc c0321d24 c045ab4c 00000114
3f20: 0046b1e0 dd0e3f80 dd0e3f4c dd0e3f38 c022d3f8 c045ab58 de4fc400 00000114
3f40: dd0e3f7c dd0e3f50 c022d62c c022d3dc c024ba80 c024b018 de4fc400 de4fc401
3f60: 0046b1e0 00000114 c0107f08 dd0e2000 dd0e3fa4 dd0e3f80 c022d7d4 c022d56c
3f80: 00000000 00000000 00000114 0046b1e0 00000005 00000004 00000000 dd0e3fa8
3fa0: c0107ce0 c022d790 00000114 0046b1e0 00000005 0046b1e0 00000114 00000000
3fc0: 00000114 0046b1e0 00000005 00000004 00000000 00000000 0046507c 000575c0
3fe0: 00000000 beaa1b78 00000000 b6f186f0 800f0010 00000005 00000000 00000000
[<c05cb044>] (__memzero) from [<c01e1aa4>] (get_page_from_freelist+0x934/0x994)
[<c01e1aa4>] (get_page_from_freelist) from [<c01e2190>] (__alloc_pages_nodemask+0xc4/0xd14)
[<c01e2190>] (__alloc_pages_nodemask) from [<c0208254>] (__pte_alloc+0x30/0x1bc)
[<c0208254>] (__pte_alloc) from [<c020af2c>] (handle_mm_fault+0x21c/0x91c)
[<c020af2c>] (handle_mm_fault) from [<c0113b30>] (do_page_fault+0x184/0x32c)
[<c0113b30>] (do_page_fault) from [<c0113dbc>] (do_translation_fault+0x2c/0xc8)
[<c0113dbc>] (do_translation_fault) from [<c0101254>] (do_DataAbort+0x48/0xc8)
[<c0101254>] (do_DataAbort) from [<c010d3b8>] (__dabt_svc+0x58/0x80)
Exception stack(0xdd0e3df8 to 0xdd0e3e40)
3de0:                                                       003c7b20 00000000
3e00: 0001e3d9 c09ba758 00000210 00000114 0009e3d9 003c7b20 c0908300 00000001
3e20: 003c7b20 dd0e3e7c dd0e3e80 dd0e3e48 c0114534 c0114430 a00f0013 ffffffff
[<c010d3b8>] (__dabt_svc) from [<c0114430>] (dma_cache_maint_page+0x58/0x128)
[<c0114430>] (dma_cache_maint_page) from [<c0114534>] (__dma_page_cpu_to_dev+0x34/0x88)
[<c0114534>] (__dma_page_cpu_to_dev) from [<c01145d0>] (arm_dma_sync_single_for_device+0x48/0x54)
[<c01145d0>] (arm_dma_sync_single_for_device) from [<c045a814>] (start_dma_transfer+0x17c/0x32c)
[<c045a814>] (start_dma_transfer) from [<c045ac9c>] (rdsp_write+0x150/0x16c)
[<c045ac9c>] (rdsp_write) from [<c022d3f8>] (__vfs_write+0x28/0x48)
[<c022d3f8>] (__vfs_write) from [<c022d62c>] (vfs_write+0xcc/0x158)
[<c022d62c>] (vfs_write) from [<c022d7d4>] (SyS_write+0x50/0x88)
[<c022d7d4>] (SyS_write) from [<c0107ce0>] (ret_fast_syscall+0x0/0x5c)
Code: e52de004 e1a0c002 e1a0e002 e2511040 (a8a0500c)
---[ end trace 0000000000000003 ]---

    Is it really a problem related to RAM?

    I just shared our length matching reports with you offline as well as some screenshots of the DDR design - could you please have a look. The trace impedances are within 55-59 ohms (depends on a layer).

    We have just checked the lengths of the BBB design that all of the lengths matching skew are within 10 mils in byte lanes instead of 25 mils as it is in the AM335X Datasheet, Rev.L, Section 7.7.2.3.6.2 DQS[x] and DQ[x] Routing Specification Table 7-69. DQS[x] and DQ[x] Routing Specification. Could you explain why is the skew shorter for each byte? Could it be helpful if we use 10 mils instead of 25 mils skew?

    What would be the next step?

    Thank you.

  • 0 in reply to Bart
    TI__Guru* 87040 points

    Bart, I'd like to verify that the spreadsheet values were correctly translated to the code.  Can you connect JTAG and run the following DSS script:

    https://git.ti.com/cgit/sitara-dss-files/am335x-dss-files/tree/am335x-ddr-analysis.dss

    Instructions for running the script can be found here:

    https://git.ti.com/cgit/sitara-dss-files/am335x-dss-files/tree/README

    Also, can you provide the source code that configures the EMIF controller and PHY.  You can share these offline if needed

    Regards,

    James

  • 0 in reply to JJD
    TI__Expert 6460 points

    Hi James,

    thank you. Please see the results attached, I shared the source code offline.

    Looking forward for your feedback. 

    Fullscreen am335x-ddr-analysis_2020-06-18_154158.txt Download 
    Skipping read of EMIF registers since EMIF clock disabled.
 * EMIF registers are not readable when in DS0 state
 * If you are attempting to enter DS0 this is normal.

************************
*** IOCTRL Registers ***
************************

CONTROL: DDR_CMD0_IOCTRL = 0x00000000
  * ddr_ba2 Pullup/Pulldown disabled
  * ddr_wen Pullup/Pulldown disabled
  * ddr_ba0 Pullup/Pulldown disabled
  * ddr_a5 Pullup/Pulldown disabled
  * ddr_ck Pullup/Pulldown disabled
  * ddr_ckn Pullup/Pulldown disabled
  * ddr_a3 Pullup/Pulldown disabled
  * ddr_a4 Pullup/Pulldown disabled
  * ddr_a8 Pullup/Pulldown disabled
  * ddr_a9 Pullup/Pulldown disabled
  * ddr_a6 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_ck and ddr_ckn
    - Slew fastest
    - Drive Strength 5 mA
  * Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]
    - Slew fastest
    - Drive Strength 5 mA
CONTROL: DDR_CMD1_IOCTRL = 0x00000000
  * ddr_a15 Pullup/Pulldown disabled
  * ddr_a2 Pullup/Pulldown disabled
  * ddr_a12 Pullup/Pulldown disabled
  * ddr_a7 Pullup/Pulldown disabled
  * ddr_ba1 Pullup/Pulldown disabled
  * ddr_a10 Pullup/Pulldown disabled
  * ddr_a0 Pullup/Pulldown disabled
  * ddr_a11 Pullup/Pulldown disabled
  * ddr_casn Pullup/Pulldown disabled
  * ddr_rasn Pullup/Pulldown disabled
  * Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn
    - Slew fastest
    - Drive Strength 5 mA
CONTROL: DDR_CMD2_IOCTRL = 0x00000000
  * ddr_cke Pullup/Pulldown disabled
  * ddr_resetn Pullup/Pulldown disabled
  * ddr_odt Pullup/Pulldown disabled
  * ddr_a14 Pullup/Pulldown disabled
  * ddr_a13 Pullup/Pulldown disabled
  * ddr_csn0 Pullup/Pulldown disabled
  * ddr_a1 Pullup/Pulldown disabled
  * Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1
    - Slew fastest
    - Drive Strength 5 mA
CONTROL: DDR_DATA0_IOCTRL = 0x00000000
  * ddr_d8 Pullup/Pulldown disabled
  * ddr_d9 Pullup/Pulldown disabled
  * ddr_d10 Pullup/Pulldown disabled
  * ddr_d11 Pullup/Pulldown disabled
  * ddr_d12 Pullup/Pulldown disabled
  * ddr_d13 Pullup/Pulldown disabled
  * ddr_d14 Pullup/Pulldown disabled
  * ddr_d15 Pullup/Pulldown disabled
  * ddr_dqm1 Pullup/Pulldown disabled
  * ddr_dqs1 and ddr_dqsn1 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs1, ddr_dqsn1
    - Slew fastest
    - Drive Strength 5 mA
  * Bits 4:0 control ddr_d[15:8], ddr_dqm1
    - Slew fastest
    - Drive Strength 5 mA
CONTROL: DDR_DATA1_IOCTRL = 0x00000000
  * ddr_d0 Pullup/Pulldown disabled
  * ddr_d1 Pullup/Pulldown disabled
  * ddr_d2 Pullup/Pulldown disabled
  * ddr_d3 Pullup/Pulldown disabled
  * ddr_d4 Pullup/Pulldown disabled
  * ddr_d5 Pullup/Pulldown disabled
  * ddr_d6 Pullup/Pulldown disabled
  * ddr_d7 Pullup/Pulldown disabled
  * ddr_dqm0 Pullup/Pulldown disabled
  * ddr_dqs0 and ddr_dqsn0 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs0, ddr_dqsn0
    - Slew fastest
    - Drive Strength 5 mA
  * Bits 4:0 control ddr_d[7:0], dqm0
    - Slew fastest
    - Drive Strength 5 mA
CONTROL: DDR_IO_CTRL = 0x00000000
  * Bit 31: DDR_RESETn controlled by EMIF.
  * Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.
CONTROL: VTP_CTRL = 0x00000000
  * VTP disabled (expected in DS0).
CONTROL: VREF_CTRL = 0x00000000
  * VREF supplied externally (typical).
CONTROL: DDR_CKE_CTRL = 0x00000000
  * CKE gated (forces pin low).
    Fullscreen memdump.txt Download 
    *** Register Dump ***

root@eppfl1:~# devmem 0x4c000000
0x40443403
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000004
0x40000004
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000008	EMIF: SDRAM_CONFIG
0x61A05332
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c00000c
0x00000000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000010
0x00000C30
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000014
0x00000C30
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000018
0x0AAAD4DB
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c00001c
0x0AAAD4DB
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000020
0x246B7FDA
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000024
0x246B7FDA
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000028
0x50FFE67F
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c00002c
0x50FFE67F
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000038	EMIF: PWR_MGMT_CTRL
0x00000000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c00003c
0x00000000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000054
0x00141414
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000058
0x8000140A
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c00005c
0x00021616
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000080
0x192F333E
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000084
0x0877FAE5
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000088
0x00010000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c00008c
0x00000000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000090
0x96454C8E
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000098
0x00050000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c00009c
0x00050000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c0000a4
0x00000000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c0000ac
0x00000000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c0000b4
0x00000000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c0000bc
0x00000000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c0000c8
0x50074BE1
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c0000d4
0x00000000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c0000d8
0x00000000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c0000dc
0x00000000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c0000e4	DDR PHY: DDR_PHY_CTRL_1
0x00100208
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c0000e8
0x00100208
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000100
0x00000000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000104
0x00000000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000108
0x00000000
root@eppfl1:~# 
root@eppfl1:~# devmem 0x4c000120
0x00000305




DDR_CMD0_IOCTRL:
root@eppfl1:~# devmem 0x44e11404
0x0000018B

DDR_CMD1_IOCTRL:
root@eppfl1:~# devmem 0x44e11408
0x0000018B

DDR_CMD2_IOCTRL:
root@eppfl1:~# devmem 0x44e1140c
0x0000018B

DDR_DATA0_IOCTR:
root@eppfl1:~# devmem 0x44e11440
0x0000018B

DDR_DATA1_IOCTR:
root@eppfl1:~# devmem 0x44e11444
0x0000018B

DDR_IO_CTRL:
root@eppfl1:~# devmem 0x44e10e04
0x00000000

VTP_CTRL:
root@eppfl1:~# devmem 0x44e10e0c
0x00000067

VREF_CTRL:
root@eppfl1:~# devmem 0x44e10e14
0x00000000

DDR_CKE_CTRL:
root@eppfl1:~# devmem 0x44e10131c
0x00000001