AM3352: TDM output

Hi Nishigata-san,

The PCM1791A TDMCA was designed for the McBSP audio peripheral.
It appears that the McASP audio peripheral on the AM335x cannot natively support the frame synch/LRCK pulse width of two BCK cycles required by TDMCA.

PCM1791A recognizes the TDMCA mode automatically when it receives an LRCK signal with a pulse duration of two BCK clocks.

McASP supports either single bit (1 BCK cycle) or single word (8-bit minimum).
Refer to SPRUH73Q Section 22.4.1.27 register AFSXCTL Register:
Bit 4 FXWID Transmit frame sync width select bit indicates the width of the transmit frame sync (AFSX) during its active period.
0h = Single bit.
1h = Single word.

In comparison, McBSP supports a frame pulse with a programmable period between sync pulses and a programmable active width specified in SRGR
 - FWID controls the active width of the frame sync pulse and can support a width of two BCK clocks.
 
There may be possible (unproven) workarounds to allow McASP to support PCM1791A TDMCA...
I describe two possible workarounds:
1) Use a separate data serializer (AXR pin) as a replacement to frame synch/LRCK signal. The data driven from this pin could mimic the two BCK clock cycle required by PCM1791A TDMCA.
2) Use hardware glue logic to extend width of frame synch/ LRCK by one additional BCK.
    
If the customer decides to try one of these workarounds, I recommend evaluating the signals with an EVM and oscilloscope.

Hope this helps,
Mark