66AK2G12: Software steps for configuring a new DDR3

Krishna Boopathy J

Part Number: 66AK2G12

Hi Team,

We are interfacing a new DDR3 part number that is different from the one that is available on the K2G evaluation board.

To configure the DDR3 and to interface it with the 66AK2G12 processor, we are using the following procedure.

1. Use the DDR3 register configuration spreadsheet tool to determine the PHY and CONFIG register values of the DDR3 controller.
2. Populate the new register values in the "\ti\board\src\evmK2G\evmK2G_ddr.c" file and include it as a part of the project.

Can you confirm if this is the expected procedure to configure a new DDR3 part with the processor.

--> NOTE : In the evmK2G_ddr.c file and the register calculation spreadsheet there are few PHY registers that we can't map with each other. Any help would be great in this regard.

And since we are migrating from 24MHz to 25MHz crystal and also with the new DDR3 part number, can the existing MLO file that we have been using be continued as it is. Or do we need to alter the MLO file to support these major changes.?

Also can you share the procedure for editing the .gel file to test these changes through JTAG as well.

Thanks in Advance.

Regards,

Krishna.

over 4 years ago

0 Krishna Boopathy J over 4 years ago

Intellectual 340 points

Broken image in the previous post.

0 Rex Chang over 4 years ago in reply to Krishna Boopathy J

TI__Guru 50170 points

Hi, Krishna,

You can start with this SPRACM0, http://www.ti.com/lit/an/spracm0/spracm0.pdf which then links to all of the related DDR collateral. There are more info in the following post, https://e2e.ti.com/support/processors/f/791/p/618247/2999168#2999168 on the DDR3 Configuration guide.

Hope these info help.

Rex

0 Krishna Boopathy J over 4 years ago in reply to Rex Chang

Intellectual 340 points

Hi Team,

For the 66AK2G12 processor, we are interfacing it with a DDR3 memory which is a different part from what is present on the EVM board.
So we used the DDR3 register calculation tool from TI, to obtain the values. And with these values we updated the evmK2G_ddr.c file in the /ti/board/src/evmK2G/ path. I have attached the updated file.

Apart from these changes is it required to updated any other files/values in the code.?

II)

Also we tried to verify the values for the EVM board too with the same tool.

We used the tool to obtain DDR3 register values for the DDR3 Ram used on the evaluation board. And we took a register dump to read the DDR3 register values during program execution.

When we compared the two, we found few changes in the following registers.

PHY Registers	Values obtained from DDR3 register tool	Value from reading the registers	Values used in Code [evmK2G_ddr.c]
DDR3_PGCR0	A8000E3F	-	not used in code
DDR3_PGCR1	0080C507	0280C525	depend on existing value
DDR3_PGCR2	00F05159	00F05159	00F05159
DDR3_PLLCR	000DC000	000DC000	DC000
DDR3_MR0	00001830	00001830	1830
DDR3_MR1	00000006	00000006	6
DDR3_MR2	00000048	8	8	(Auto self-refresh not enabled in code)
DDR3_MR3	00000000	-	not used in code
DDR3_DTPR0	6D147744	6D147744	6D147744
DDR3_DTPR1	32845A80	32845A80	32845A80
DDR3_DTPR2	50023600	50023600	50023600
DDR3_PTR0	42C21590	42C21590	42C21590
DDR3_PTR1	D05612C0	D05612C0	D05612C0
DDR3_PTR2	00083DEF	00083DEF	0
DDR3_PTR3	0914111D	0904111D	0904111D	DDR3 = CKE high time to first command (tRFC + 10 ns or 5 tCK, whichever is bigger)
DDR3_PTR4	0859A072	0859A072	0859A072
DDR3_DCR	0000040B	0000040B	depend on existing value
DDR3_DTCR	710035C7	710035C7	710035C7
DDR3_DXCCR	44181884	-	not used in code
DDR3_ZQ0CR1	0001005D	0001005D	0001005D
DDR3_ZQ1CR1	0001005B	0001005B	0001005B
DDR3_ZQ2CR1	0001005B	0	0001005B

Similarly for EMIF registers, we found two registers has slightly different values.

Control Registers	Value obtained from DDR3 register tool	Values in Code
DDR_SDCFG	62005660	62005662	(LSB–00-256 word page) (LSB–10-512 word page)
DDR_SDTIM1	0E4C6843	0E4C6843
DDR_SDTIM2	00001CC6	00001CC6
DDR_SDTIM3	3241FF32	323DFF32	These bits specify the minimum number of fDDR3_CLKOUT cycles from a selef-refresh exit to a command that does not require locked DLL minus 1
DDR_SDTIM4	533F08AF	533F08AF
DDR_ZQCFG	70073200	70073200
DDR_SDRFC (normal)	00001044	1044

Will these change in values affect the performance/function of DDR3.

Can you please confirm if we can use the value from the DDR3 calculation toll as it is.?

With Thanks,
Krishna

0 Tom Johnson 16214 over 4 years ago in reply to Krishna Boopathy J

TI__Mastermind 46460 points

Krishna,

Detailed information to answer your questions is available in the linked documents. The KeyStone II DDR3 Interface Bring-Up Application Report (SPRACM0) explains the sequence of steps needed to commission a DDR interface for this type of DDR PHY. (All KS-II devices have the same DDR PHY.) This document then points you to the Keystone II DDR3 Initialization Application Report (SPRABX7) which explains the programming sequence required at start-up to initialize the DDR interface. It explains that some registers are not used and that some must be updated using READ-MODIFY-WRITE with a mask so that existing values do not get changed. This Initialization Application Report is the companion document to the REG_CALC worksheet. Detailed explanation for all of the PHY registers is contained in the Keystone II Architecture DDR3 Memory Controller User's Guide (SPRUHN7C).

The expectation is that you can use values from the datasheet for the replacement SDRAM to updated the REG_CALC worksheet according to its directions. Then these values can be ported into the initialization code. The new values can also be validated by updating the GEL file and initializing the DDR using the GEL file and CCS.

Tom

0 Tom Johnson 16214 over 4 years ago in reply to Tom Johnson 16214

TI__Mastermind 46460 points

Krishna,

Have you made any progress with your bring-up? Please let us know. Otherwise we will close this thread.

Tom

Processors

Processors forum

66AK2G12: Software steps for configuring a new DDR3