• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 97 subscribers
  • Views 565 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6678: DDR access conflict

Nancy Wang
Expert 8210 points

Part Number: TMS320C6678
Other Parts Discussed in Thread: SYSBIOS

Hi,

Customer using FPGA write to DDR(tms320c6678) via SRIO, and DSP need to access DDR(different address) in the meanwhile. But SRIO always be blocked unless he disable the DSP's W/R function.

How to solve the problem of access conflict?

  • 0
    TI__Guru* 95265 points

    Hi,

    You may check the Keystone I DDR3 user guide (https://www.ti.com/lit/ug/sprugv8e/sprugv8e.pdf), section 2.6 to see if that helps. Also, >>>>But SRIO always be blocked unless he disable the DSP's W/R function.>>>> is this a SYSBIOS application and the SRIO task is lower so blocked by the high priority ones, like your CPU access to DDR? What block means here?

    Regards, Eric

  • 0 in reply to lding
    TI__Expert 8210 points

    Hi,

    It's sys/bios application.

    There is only one task (CPU access to DDR) in application. SRIO directly transfers the data from FPGA side to DDR via DIO.

    When dsp access to DDR, the control of the DDR bus seems occupied by the DSP, and at this time if fpga writes to DDR through SRIO will be blocked.

    Is there a conflict when two hosts access DDR at the same time, and if so, is there any way to avoid this problem? How to set priority?

  • 0 in reply to Nancy Wang
    TI__Guru* 95265 points

    Hi,

    I don't think we understand the issue right. In many SRIO applications, there is a data transfer in/out of DDR3 by SRIO. Meanwhile the program runs in DDR3, also Ethernet W/R packets in DDR3. We never heard of any conflict in DDR3. The bandwidth of DDR3 is 1333*8 = 10664MB/s, this is much higher than the SRIO (e.g. 5Gb/s * num of lanes/8).

    TI has SRIO test examples, http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_device_drv.html#srio. You can do a DSP CPU access of DDR3 when SRIO is transferring. Are you see issues based on this?  

    You can refer to 2.6.4 Class of Service in DDR3 user guide if you want to try the setting.

    Regards, Eric

  • 0 in reply to lding
    Guru 13202 points

    I would second observation reported by Eric. For years we have a system with portions of code, secondary heap, and data buffers in DDR3 and that memory is written/read by PCIe either with EDMA3 of processor or DMA engine on FPGA side - it never was an issue. The way PCIe reaches DDR3 is technically same to SRIO.