TMS320C6678: SRIO-to-DDR3 write can't start when EDMA is copying data in DDR3

Feng

Part Number: TMS320C6678

Hi all,

We met a problem that when the EDMA is copying data in DDR3, the SRIO-to-DDR3 write can not start.

1. Would the explanation be: because EDMA has higher bus priority than SRIO, so SRIO write can not start when the bus is held by the EDMA?

2. If this is the case, then if we set EDMA bus priority higher than SRIO,can we solve the problem?

3. Considering the case that the SRIO-to-DDR3 write comes during EDMA is copying data in DDR3, so the EDMA will hold until SRIO finishes writing and then resume, if the SRIO has higher priority?

4. If so, how can we set the EDMA bus priority than SRIO's?

Thanks,

Feng

over 5 years ago

0 lding over 5 years ago

TI__Guru* 95265 points

Hi,

Please see this https://e2e.ti.com/support/processors/f/791/t/341611 for SRIO priority setting.

Regards, Eric

0 Feng over 5 years ago in reply to lding

Expert 2985 points

Thanks for your reply, Eric.

We tried this, but it doesn't work. Maybe the issue is not about the bus priority.

Let me ask the question in this way.

1. Assuming the FPGA is writing the DDR3 via SRIO, could EDMA DDR3-to-DDR3 writing execution be delayed until SRIO-to-DDR3 writing is done?

2. Assuming the EDMA is working on DDR3-to-DDR3 write, could a FPGA SRIO-to-DDR3 write be delayed until the EDMA is done?

We thought we have met a situation like this:

3. The EDMA is working on DDR3-to-DDR3 write (it may take a little while until finish), FPGA SRIO-to-DDR3 write can not start. And if EDMA is not working, SRIO can start.

We think that this is because the priority of SRIO is higher than EDMA. But it may not be true. Do you have any ideas about this?

Thanks a lot!

Feng

0 lding over 5 years ago in reply to Feng

TI__Guru* 95265 points

Feng,

Is it possible that EDMA write and SRIO write are in two separate RTOS tasks, and the EDMA task has a higher priority and blocked the SRIO from the OS level?

Another thing to check is the EDMA (https://www.ti.com/lit/ug/sprugs5b/sprugs5b.pdf) usage of QUEPRI and RDRATE registers, can you lower them to see if helps?

Regards, Eric

0 Feng over 5 years ago in reply to lding

Expert 2985 points

I see. I'll check this. Thanks, Eric.

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TMS320C6678: SRIO-to-DDR3 write can't start when EDMA is copying data in DDR3