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C6457 EMIF (64-bit data) Interface to FPGA

TommyG
Genius 13045 points

I have a question on the C6457 EMIF information in the EMIF UG (SPRUGK2).  It is not clear to me how the Byte Enable signaling works for asynchronous interface.  I am looking at sec 4.3 and 4.4.  It is not clear if both sections are discussing the same data bus width. 

Sec 4.3 discusses async Reads and states that BE[7:0] become active and Fig 8 shows all BE signals low.  Will this be true for any size data access, or is this example assuming 64-bit data)?  What would BE signaling look like for 32-bit or 16-bit data Reads.  Would FPGA be able to determine the data width being requested by the 6457 from the signaling it receives (like BE lines)?

Sec 4.4 discusses async Writes and states that BE[3:0] become valid.  Fig 9 shows BE[7:0] to be HI or LO.  Is this because the Write example is only for 32-bit access? 

Can't quite figure out how the async interface functions from the description in Sec 4 of the EMIF UG.  Can you provide some clarification?

Thanks.

  • 0
    TI__Guru* 84110 points

    TommyG,

    I do not have first-hand knowledge of this, but I am pretty sure these answers are right. Maybe we can get a real expert to at least say "yes, that is right".

    For reads, Section 4.3 makes a distinction between active and valid. BE[7:0] go active and EA/BA go valid. At the end of the hold, BE lines go inactive

    I am pretty sure that for reads, no external byte distinction is made because the EMIF assumes any read is from a memory device and that device should not care if the DSP is only using part of the bus width. So for reads, all used BE lines will go low, active.

    For writes, Section 4.4 says the BE lines go valid like the EA/BA lines. It forgets to mention BE at the end of the hold period, but it should say they become invalid then. And Section 4.4 should say BE[7:0] rather than 3:0. Probably a cut-and-paste error when it was written.

    In Figure 4 on page 12, Note B says which BE and ED lines are used for the different bus width configurations. The unused BE lines should be ignored, of course.

    Unfortunately, the datasheet does not make any mention of the BE lines in the EMIFA Async read/write timings in section 7.10.3. That is a big oversight. But the version I have SPRS582B still says Product Preview, which also is odd.

    I hope this helps a little.

    Regards,
    RandyP

  • 0 in reply to RandyP
    TI__Genius 13045 points

    Randy,

    Thanks for the feedback.  I appreciate your insights.

    TommyG