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[OMAP-L138] Customize cpufreq to allow lower operating frequency

GrantHatamosa
Expert 1930 points
Other Parts Discussed in Thread: OMAP-L138, OMAPL138

We are trying to get to the lowest operating frequency possible when the OMAP-L138 is idle but not in sleep.

As indicated by http://processors.wiki.ti.com/index.php/OMAP-L1_Linux_Drivers_Usage#Power_Management we can use cpufreq to adjust the operating frequency of the OMAP-L138 on the fly. However the current implementation only allows us to adjust to as low as 96MHz.

For this reason I would like to ask the following questions:

1. If we want to adjust to the lowest possible operating frequency what value should that be without causing any issues on the other parts of the system?

2. Can you point us to a resource that will help us understand how to change the cpufreq code to add another frequency to support?

  • 0
    Expert 1930 points

    i figured out that to add new frequency settings supported by cpufreq that you need to modify ./arch/arm/mach-davinci/da850.c

     

    now i just need to know what frequency is valid.

    any input from TI?

  • 0 in reply to GrantHatamosa
    TI__Guru* 82595 points

    Hi Grant

    You can run the device in bypass frequency (CLKIN frequency) and even lower (KHz range). The 100/96 MHz is the "maximum" operating frequency at CVDD 1.0V. The realistic minimum frequency will be driven by your application and peripheral usage. Modules that derive IO clocks from internal (device) clock source, and will depend on PLL0_SYSCLKn frequency etc, as you go down in frequency you would need to ensure that those interfaces work as per your expectations in terms of performance and clock rates etc.

     

    Some additional pointers

    1. The "max" frequencies are at all voltage points is documented in Table 6-5 in the datasheet
    2. The OMAPL138 System Guide , chapter 7 (Clocking) should be helpful for you to understand the clock tree/PLL sources etc for various peripherals. 
    3. You need to be careful if you plan to use DDR2/mDDR memory at lower frequencies. Typically PLL1 (which sources the mDDR/DDR2 controller) needs to have the pll multipliers and dividers such that minimum requirements for DDR2/mDDR are met (as specified in Table 6-25, in the datasheet) 
    4. If you want to run the CPUs at lower frequency (sourced by PLL0) and keep some other modules un-affected, on OMAPL138  ECAPs, UART1/2, Timer64P2/3, eHRPWMs, McBSPs, McASP0, SPI1can alternatively be sourced by PLL1_SYSCLK2 (default source is PLL0_SYSCLK2). Details in Clocking chapter 7 in the system guide.

    Hope this helps.

    Regards

    Mukul