Hi,
One of my colleagues has designed a board using TMS320C6745. The designed board is in my responsibility from now on. I have some problems, that I can not solve, with C6745. When I check the schematics and layout, they do seem OK. I was unable to participate during the design process, so I am not a master about the design. That is why, I need profeccional help.
A brief information about the problem;
C6745 crashes randomly. I do not load a complicated program. The program just initializes the DSP and sets and resets a specific GPIO0 pin.
I share the board design, my code and error message of CCS3.3 Platinium. I use Spectrum Digitals XDS510USB PLUS.
Any help will be appreciated.
here is design;
http://img145.imageshack.us/i/jtag.jpg/
http://img268.imageshack.us/i/dspx.jpg/
here is ccs3.3 platinium error window;
http://img153.imageshack.us/i/86491891.jpg/
P.S. sorry for the links. I can not open add image tool of TI's webpage.
here is my code;
(I do not use a .gel file. all necessary things are in bsp.c)
/*----bcp.c----*/
/*
*********************************************************************************************************
* P2 BOARD SUPPORT
*
* (c) Copyright 2010; Havelsan A.S.; Ankara, Turkiye
*
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* BOARD SUPPORT PACKAGE
*
* Texas Instruments TMX320C6745PTP3
* on the
*
* Filename : bsp.c
* Version : V1.00
*********************************************************************************************************
*/
#include "bsp.h"
/* ------------------------------------------------------------------------ *
* *
* Setup_System_Config( ) *
* Configure PINMUX and other system module registers *
* *
* ------------------------------------------------------------------------ */
void P2_Config_init()
{
KICK0R = 0x83e70b13; // Kick0 register + data (unlock)
KICK1R = 0x95a4f1e0; // Kick1 register + data (unlock)
/*
PINMUX0 = 0x11111108; // EMIFB, Check EMU0/RTCK
PINMUX1 = 0x11111111; // EMIFB
PINMUX2 = 0x01111111; // EMIFB
PINMUX3 = 0x00000000; // EMIFB not 32 bit -->16bit SDRAM
PINMUX4 = 0x00000000; // EMIFB not 32 bit -->16bit SDRAM
PINMUX5 = 0x11111110; // EMIFB
PINMUX6 = 0x11111111; // EMIFB
PINMUX7 = 0x11111111; // EMIFB, SPI0
PINMUX8 = 0x28811888; // UART2, McASP1, I2C0, I2C1 //0x21111111 0x2112211
PINMUX9 = 0x88888802; // RMII CLK, McASP0, USB_DRVVBUS, UART2 // 0x11011112
PINMUX10 = 0x88888880; // RMII/ McASP0 // 0x22222221
PINMUX11 = 0x88881188; // McASP1, UART1, McASP0, MDIO (last 2 digits 0x22 for MDIO instead of GPIO) //0x11112222 0x11111122
PINMUX12 = 0x88888880; // McASP0 / McASP1 // 0x11111111
PINMUX13 = 0x88888888; // SD / McASP1 // 0x22111111 0x88111111
PINMUX14 = 0x88888888; // SD / EMIFA // 0x88888888 0x88222222
PINMUX15 = 0x88888888; // SD / EMIFA // 0x21888888
PINMUX16 = 0x88888888; // SD / EMIFA //0x11111112
PINMUX17 = 0x00088888; // EMIFA //0x00100111
PINMUX18 = 0x00888080; // EMIFA //0x11111111
PINMUX19 = 0x00000008; // EMIFA //0x00000001
PINMUX0=0x00000000;
PINMUX1=0x00000000;
PINMUX2=0x00000000;
PINMUX3=0x00000000;
PINMUX4=0x00000000;
PINMUX5=0x00000000;
PINMUX6=0x00000000;
PINMUX7=0x22000000;
PINMUX8=0x00011000;
PINMUX9=0x00000000;
PINMUX10=0x00000000;
PINMUX11=0x00000000;
PINMUX12=0x00000000;
PINMUX13=0x80000000;
PINMUX14=0x00000088;
PINMUX15=0x00000000;
PINMUX16=0x00000000;
PINMUX17=0x00000000;
PINMUX18=0x00000000;
PINMUX19=0x00000000;
*/
PINMUX0=0x00000000;
PINMUX1=0x00000000;
PINMUX2=0x00000000;
PINMUX3=0x00000000;
PINMUX4=0x00000000;
PINMUX5=0x00000000;
PINMUX6=0x00000000;
PINMUX7=0x22000000;
PINMUX8=0x20011000;
PINMUX9=0x00000002;
PINMUX10=0x00000000;
PINMUX11=0x00001100;
PINMUX12=0x00000000;
PINMUX13=0x80000000;
PINMUX14=0x00000088;
PINMUX15=0x00000000;
PINMUX16=0x00000000;
PINMUX17=0x00000000;
PINMUX18=0x00000000;
PINMUX19=0x00000000;
}
void P2_PLL_init()
{
int i = 0;
Uint32 DIV45_EN = 1;
Uint32 CLKMODE = 0;
Uint32 PLLM = 24;
Uint32 POSTDIV = 1;
Uint32 PLLDIV3 = 2;
Uint32 PLLDIV5 = 5;
Uint32 PLLDIV7 = 7;
// Moved step 2c and 2d to step 0
/*Set PLLEN=0 and PLLRST=0, Reset the PLL*/
PLL0_PLLCTL &= 0xFFFFFFFE; /*PLL BYPASS MODE*/
/*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
for(i=0; i<PLLEN_MUX_SWITCH; i++) {;} /*Make PLLEN_MUX_SWITCH as bootpacket*/
/*Select the Clock Mode bit 8 as External Clock or On Chip Oscilator*/
PLL0_PLLCTL &= 0xFFFFFEFF;
PLL0_PLLCTL |= (CLKMODE<<8); /* Make CLKSRC as BootPacket to pass the value*/
/*Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR*/
PLL0_PLLCTL &= 0xFFFFFFDF;
/*PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Primus*/
PLL0_PLLCTL &= 0xFFFFFDFF;
/* Clear PLLRST bit to 0 -Reset the PLL */
PLL0_PLLCTL &= 0xFFFFFFF7;
/*Disable the PLL output*/
PLL0_PLLCTL |= 0x10;
/*PLL initialization sequence*/
/*Power up the PLL- PWRDN bit set to 0 to bring the PLL out of power down bit*/
PLL0_PLLCTL &= 0xFFFFFFFD;
/*Enable the PLL from Disable Mode PLLDIS bit to 0 - This is step is not required for Primus*/
PLL0_PLLCTL &= 0xFFFFFFEF;
/*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
// for(i=0; i<PLL_STABILIZATION_TIME; i++) {;} /* Make PLL_STABILIZATION_TIME as bootpacket*/
/*Program the required multiplier value in PLLM*/
PLL0_PLLM = PLLM; /* Make PLLMULTIPLEIR as bootpacket*/
/*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
PLL0_POSTDIV = 0x8000 | POSTDIV; /* Make POSTDIV as bootpacket*/
/*If Necessary program the PLLDIVx*/
/*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
while(PLL0_PLLSTAT & 0x1==1){}
/*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
PLL0_PLLDIV3 = 0x8000 | PLLDIV3; /* Make PLLDIV3 as bootpacket, do it for other PLLDIVx to if required*/
PLL0_PLLDIV5 = 0x8000 | PLLDIV5; /* Make PLLDIV5 as bootpacket, do it for other PLLDIVx to if required*/
PLL0_PLLDIV7 = 0x8000 | PLLDIV7; /* Make PLLDIV7 as bootpacket, do it for other PLLDIVx to if required*/
/*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
PLL0_PLLCMD |= 0x1;
/*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
while(PLL0_PLLSTAT & 0x1==1) { }
/*Wait for PLL to reset properly. See PLL spec for PLL reset time - This step is not required here -step11*/
// for(i=0; i<PLL_RESET_TIME_CNT; i++) {;} /*128 MXI Cycles*/ /*Make PLL_RESET_TIME_CNT as boot packet*/
/*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
PLL0_PLLCTL |= 0x8;
/*Wait for PLL to lock. See PLL spec for PLL lock time*/
for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;} /*Make PLL_LOCK_TIME_CNT as boot Packet*/
/*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
PLL0_PLLCTL |= 0x1;
KICK0R = 0x83e70b13; // Kick0 register + data (unlock)
KICK1R = 0x95a4f1e0; // Kick1 register + data (unlock)
if(DIV45_EN==1)
{
CFGCHIP3 |= 0x4; // Enable 4.5 divider PLL
}
// CFGCHIP3 |= 0x1; // Select 4.5 divider for EMIFB clock source only (not EMIFA)
}
void P2_PLL2_init()
{
int i = 0;
Uint32 DIV45_EN = 1;
Uint32 CLKMODE = 0;
Uint32 PLLM = 24;
Uint32 POSTDIV = 1;
Uint32 PLLDIV3 = 2;
Uint32 PLLDIV5 = 5;
Uint32 PLLDIV7 = 7;
// Moved step 2c and 2d to step 0
/*Set PLLEN=0 and PLLRST=0, Reset the PLL*/
PLL0_PLLCTL &= 0xFFFFFFFE; /*PLL BYPASS MODE*/
/*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
for(i=0; i<PLLEN_MUX_SWITCH; i++) {;} /*Make PLLEN_MUX_SWITCH as bootpacket*/
/*Select the Clock Mode bit 8 as External Clock or On Chip Oscilator*/
PLL0_PLLCTL &= 0xFFFFFEFF;
PLL0_PLLCTL |= (CLKMODE<<8); /* Make CLKSRC as BootPacket to pass the value*/
/*Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR*/
PLL0_PLLCTL &= 0xFFFFFFDF;
/*PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Primus*/
PLL0_PLLCTL &= 0xFFFFFDFF;
/* Clear PLLRST bit to 0 -Reset the PLL */
PLL0_PLLCTL &= 0xFFFFFFF7;
/*Disable the PLL output*/
PLL0_PLLCTL |= 0x10;
/*PLL initialization sequence*/
/*Power up the PLL- PWRDN bit set to 0 to bring the PLL out of power down bit*/
PLL0_PLLCTL &= 0xFFFFFFFD;
/*Enable the PLL from Disable Mode PLLDIS bit to 0 - This is step is not required for Primus*/
PLL0_PLLCTL &= 0xFFFFFFEF;
/*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
// for(i=0; i<PLL_STABILIZATION_TIME; i++) {;} /* Make PLL_STABILIZATION_TIME as bootpacket*/
/*Program the required multiplier value in PLLM*/
PLL0_PLLM = PLLM; /* Make PLLMULTIPLEIR as bootpacket*/
/*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
PLL0_POSTDIV = 0x8000 | POSTDIV; /* Make POSTDIV as bootpacket*/
/*If Necessary program the PLLDIVx*/
/*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
while(PLL0_PLLSTAT & 0x1==1){}
/*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
PLL0_PLLDIV3 = 0x8000 | PLLDIV3; /* Make PLLDIV3 as bootpacket, do it for other PLLDIVx to if required*/
PLL0_PLLDIV5 = 0x8000 | PLLDIV5; /* Make PLLDIV5 as bootpacket, do it for other PLLDIVx to if required*/
PLL0_PLLDIV7 = 0x8000 | PLLDIV7; /* Make PLLDIV7 as bootpacket, do it for other PLLDIVx to if required*/
/*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
PLL0_PLLCMD |= 0x1;
/*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
while(PLL0_PLLSTAT & 0x1==1) { }
/*Wait for PLL to reset properly. See PLL spec for PLL reset time - This step is not required here -step11*/
// for(i=0; i<PLL_RESET_TIME_CNT; i++) {;} /*128 MXI Cycles*/ /*Make PLL_RESET_TIME_CNT as boot packet*/
/*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
PLL0_PLLCTL |= 0x8;
/*Wait for PLL to lock. See PLL spec for PLL lock time*/
for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;} /*Make PLL_LOCK_TIME_CNT as boot Packet*/
/*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
PLL0_PLLCTL |= 0x1;
KICK0R = 0x83e70b13; // Kick0 register + data (unlock)
KICK1R = 0x95a4f1e0; // Kick1 register + data (unlock)
if(DIV45_EN==1)
{
CFGCHIP3 |= 0x4; // Enable 4.5 divider PLL
}
// CFGCHIP3 |= 0x1; // Select 4.5 divider for EMIFB clock source only (not EMIFA)
}
void P2_setup_PLL( Uint8 CLK, Uint8 MLP )
{
unsigned int* pll_ctl = ( unsigned int* )( 0x01c11100 );
unsigned int* pll_pllm = ( unsigned int* )( 0x01c11110 );
unsigned int* pll_cmd = ( unsigned int* )( 0x01c11138 );
unsigned int* pll_postdiv = ( unsigned int* )( 0x01c11128 );
unsigned int* pll_bpdiv = ( unsigned int* )( 0x01c1112c );
unsigned int* pll_div1 = ( unsigned int* )( 0x01c11118 );
unsigned int* pll_div2 = ( unsigned int* )( 0x01c1111c );
unsigned int* pll_div3 = ( unsigned int* )( 0x01c11120 );
unsigned int* pll_div4 = ( unsigned int* )( 0x01c11160 );
unsigned int* pll_div5 = ( unsigned int* )( 0x01c11164 );
unsigned int* pll_div6 = ( unsigned int* )( 0x01c11168 );
unsigned int* pll_div7 = ( unsigned int* )( 0x01c1116c );
unsigned int* pll_div8 = ( unsigned int* )( 0x01c11170 );
unsigned int* pll_div9 = ( unsigned int* )( 0x01c11174 );
int pll0_freq = 24 * ( MLP + 1 );
/*
* Step 1 - Set clock mode
*/
if ( CLK == 0 )
*pll_ctl &= ~0x0100; // Onchip Oscillator
else
*pll_ctl |= 0x0100; // External Clock
/*
* Step 2 - Set PLL to bypass
* - Wait for PLL to stabilize
*/
*pll_ctl &= ~0x0020;
*pll_ctl &= ~0x0001;
P2_wait( 150 );
/*
* Step 3 - Reset PLL
*/
*pll_ctl |= 0x0008;
/*
* Step 4 - Disable PLL
* Step 5 - Powerup PLL
* Step 6 - Enable PLL
* Step 7 - Wait for PLL to stabilize
*/
*pll_ctl |= 0x0010; // Disable PLL
P2_wait( 150 );
*pll_ctl &= ~0x0002; // Power up PLL
P2_wait( 150 );
*pll_ctl &= ~0x0010; // Enable PLL
P2_wait( 150 ); // Wait for PLL to stabilize
/*
* Step 8 - Load PLL multiplier
*/
*pll_pllm = MLP & 0x3f;
/*
* Step 9 - Set PLL post dividers
*/
*pll_postdiv= 0x8000 | 1; // Post divider
*pll_div3 = 0x8003; // added 23.10.2010
*pll_div5 = 0x8005; //0x8001 original
*pll_div7 = 0x8007; // added 23.10.2010
*pll_cmd |= 0x0001; // GO
P2_wait( 2000 );
/*
* Step 10 - Wait for PLL to reset ( 2000 cycles )
* Step 11 - Release from reset
*/
P2_wait( 20000 );
*pll_ctl &= ~0x0008;
/*
* Step 12 - Wait for PLL to re-lock ( 2000 cycles )
* Step 13 - Switch out of BYPASS mode
*/
P2_wait( 2000000 );
*pll_ctl |= 0x0001;
// Enable 4.5X divider
KICK0R = 0x83e70b13; // Kick0 register + data (unlock)
KICK1R = 0x95a4f1e0; // Kick1 register + data (unlock)
CFGCHIP3 |= 0x4; // Enable 4.5 divider PLL
pll0_freq = 24 * ( ( *pll_pllm & 0x3f ) + 1 ) / 2;
}
void P2_PSC0_init( Uint32 PD, Uint32 LPSC_num )
{
*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0003;
PSC0_PTCMD = 0x1<<PD;
while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) ; /*Wait for power state transition to finish*/
while( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) !=0x3);
}
void P2_PSC1_init( Uint32 PD, Uint32 LPSC_num )
{
*(unsigned int*) (PSC1_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC1_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0003;
PSC1_PTCMD = 0x1<<PD;
while( (PSC1_PTSTAT & (0x1<<PD) ) !=0) ; /*Wait for power state transition to finish*/
while( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) !=0x3);
}
void P2_Pwr_init()
{
P2_PSC0_init(0, 0);
P2_PSC0_init(0, 1);
P2_PSC0_init(0, 2);
P2_PSC0_init(0, 3);
P2_PSC0_init(0, 4);
P2_PSC0_init(0, 5);
P2_PSC0_init(0, 6);
P2_PSC0_init(0, 8);
P2_PSC0_init(0, 9);
P2_PSC0_init(0, 10);
P2_PSC0_init(0, 11);
P2_PSC0_init(0, 12);
P2_PSC0_init(0, 13);
P2_PSC1_init(0, 1);
P2_PSC1_init(0, 2);
P2_PSC1_init(0, 3);
P2_PSC1_init(0, 4);
P2_PSC1_init(0, 5);
P2_PSC1_init(0, 7);
P2_PSC1_init(0, 8);
P2_PSC1_init(0, 9);
P2_PSC1_init(0, 10);
P2_PSC1_init(0, 11);
P2_PSC1_init(0, 12);
P2_PSC1_init(0, 13);
P2_PSC1_init(0, 16);
P2_PSC1_init(0, 17);
P2_PSC1_init(0, 20);
P2_PSC1_init(0, 21);
P2_PSC1_init(0, 24);
P2_PSC1_init(0, 25);
P2_PSC1_init(0, 26);
P2_PSC1_init(0, 31);
}
void P2_Uart_init( Uint8 Port, Uint32 Baudrate )
{
Uint16 clr_byte;
Uint32 divider;
divider = 14745600 / ( Baudrate * 16);
switch ( Port )
{
case 0:
UART0_PWREMU_MGMT = 0;
P2_wait( 1000 );
UART0_DLL = (divider & 0xff);
UART0_DLH = (divider >> 8);
UART0_FCR = 0x0007;
P2_wait( 100 );
UART0_FCR = 0x0000;
UART0_IER = 0x0007;
UART0_LCR = 0x0003;
UART0_MCR = 0x0000;
UART0_PWREMU_MGMT = 0xE001;
clr_byte = UART0_THR;
break;
case 1:
UART1_PWREMU_MGMT = 0;
P2_wait( 1000 );
UART1_DLL = (divider & 0xff);
UART1_DLH = (divider >> 8);
UART1_FCR = 0x0007;
P2_wait( 100 );
UART1_FCR = 0x0000;
UART1_IER = 0x0007;
UART1_LCR = 0x0003;
UART1_MCR = 0x0000;
UART1_PWREMU_MGMT = 0xE001;
clr_byte = UART1_THR;
break;
case 2:
UART2_PWREMU_MGMT = 0;
P2_wait( 1000 );
UART2_DLL = (divider & 0xff);
UART2_DLH = (divider >> 8);
UART2_FCR = 0x0007;
P2_wait( 100 );
UART2_FCR = 0x0000;
UART2_IER = 0x0007;
UART2_LCR = 0x0003;
UART2_MCR = 0x0000;
UART2_PWREMU_MGMT = 0xE001;
clr_byte = UART2_THR;
break;
default:
break;
}
}
void P2_Uart_putchar( Uint8 Port, Uint8 Data )
{
switch ( Port )
{
case 0:
UART0_THR = Data;
while(!(UART0_LSR & 0x60));
break;
case 1:
UART1_THR = Data;
while(!(UART1_LSR & 0x60));
break;
case 2:
UART2_THR = Data;
while(!(UART2_LSR & 0x60));
break;
default:
break;
}
}
Int8 P2_Uart_getchar( Uint8 Port )
{
Uint8 Data;
Uint8 Temp;
switch ( Port )
{
case 0:
// while(!(UART0_LSR & 0x1));
Temp=UART0_LSR;
while(!(Temp & 0x1))
{
Temp=UART0_LSR;
}
Data = UART0_THR;
// Temp=UART0_LSR;
return (Data);
break;
case 1:
Temp=UART1_LSR;
while(!(Temp & 0x1))
{
Temp=UART1_LSR;
}
Data = UART1_THR;
return (Data);
break;
case 2:
Temp=UART2_LSR;
while(!(Temp & 0x1))
{
Temp=UART2_LSR;
}
Data = UART2_THR;
return (Data);
break;
default:
break;
}
}
void P2_Uart_send_data( Uint8 Port, Uint8 *BufferPtr, Uint16 Length )
{
switch ( Port )
{
case 0:
while ( Length != 0 )
{
while(!(UART0_LSR & 0x60));
P2_Uart_putchar( 0, *BufferPtr);
BufferPtr++;
Length--;
}
break;
case 1:
break;
case 2:
break;
default:
break;
}
}
void P2_wait( Uint32 delay )
{
Uint32 i;
for( i = 0 ; i < delay ; i++ ){}
}
/*----bsp.h----*/
/*
*********************************************************************************************************
* P2 BOARD SUPPORT
*
* (c) Copyright 2010; Havelsan A.S.; Ankara, Turkiye
*
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* BOARD SUPPORT PACKAGE
*
* Texas Instruments TMX320C6745PTP3
* on the
*
* Filename : bsp.h
* Version : V1.00
*********************************************************************************************************
*/
#ifndef BSP_
#define BSP_
#define MAIN_OSC_FRQ 24000000L
/* ------------------------------------------------------------------------ *
* *
* Variable types *
* *
* ------------------------------------------------------------------------ */
#define Uint32 unsigned int
#define Uint16 unsigned short
#define Uint8 unsigned char
#define Int32 int
#define Int16 short
#define Int8 char
/* ------------------------------------------------------------------------ *
* *
* Software Breakpoint code *
* Uses inline assembly command *
* *
* ------------------------------------------------------------------------ */
#define SW_BREAKPOINT asm( " SWBP 0" );
/* ------------------------------------------------------------------------ *
* *
* AEMIF Controller *
* *
* ------------------------------------------------------------------------ */
#define AEMIF_BASE 0x68000000
#define AEMIF_AWCCR *( volatile Uint32* )( AEMIF_BASE + 0x04 )
#define AEMIF_A1CR *( volatile Uint32* )( AEMIF_BASE + 0x10 )
#define AEMIF_A2CR *( volatile Uint32* )( AEMIF_BASE + 0x14 )
#define AEMIF_A3CR *( volatile Uint32* )( AEMIF_BASE + 0x18 )
#define AEMIF_A4CR *( volatile Uint32* )( AEMIF_BASE + 0x1C )
#define AEMIF_EIRR *( volatile Uint32* )( AEMIF_BASE + 0x40 )
#define AEMIF_EIMR *( volatile Uint32* )( AEMIF_BASE + 0x44 )
#define AEMIF_EIMSR *( volatile Uint32* )( AEMIF_BASE + 0x48 )
#define AEMIF_EIMCR *( volatile Uint32* )( AEMIF_BASE + 0x4C )
#define AEMIF_NANDFCR *( volatile Uint32* )( AEMIF_BASE + 0x60 )
#define AEMIF_NANDFSR *( volatile Uint32* )( AEMIF_BASE + 0x64 )
#define AEMIF_NANDECC2 *( volatile Uint32* )( AEMIF_BASE + 0x70 )
#define AEMIF_NANDECC3 *( volatile Uint32* )( AEMIF_BASE + 0x74 )
#define AEMIF_NANDECC4 *( volatile Uint32* )( AEMIF_BASE + 0x78 )
#define AEMIF_NANDECC5 *( volatile Uint32* )( AEMIF_BASE + 0x7C )
#define AEMIF_MAX_TIMEOUT_8BIT 0x3FFFFFFC
#define AEMIF_MAX_TIMEOUT_16BIT 0x3FFFFFFD
#define EMIF_CS2 2
#define EMIF_CS3 3
#define EMIF_CS4 4
#define EMIF_CS5 5
#define EMIF_CS0_BASE 0x02000000
#define EMIF_CS1_BASE 0x04000000
#define EMIF_NAND_MODE 1
#define EMIF_NORMAL_MODE 0
/* ------------------------------------------------------------------------ *
* *
* Device System Controller *
* *
* ------------------------------------------------------------------------ */
#define SYS_BASE 0x01C14000
#define REVID *(unsigned int*)(SYS_BASE + 0x000)
#define DIEIDR0 *(unsigned int*)(SYS_BASE + 0x008)
#define DIEIDR1 *(unsigned int*)(SYS_BASE + 0x00C)
#define DIEIDR2 *(unsigned int*)(SYS_BASE + 0x010)
#define DIEIDR3 *(unsigned int*)(SYS_BASE + 0x014)
#define DEVIDR0 *(unsigned int*)(SYS_BASE + 0x018)
#define DEVIDR1 *(unsigned int*)(SYS_BASE + 0x01C)
#define BOOTCFG *(unsigned int*)(SYS_BASE + 0x020)
#define CHIPREVIDR *(unsigned int*)(SYS_BASE + 0x024)
#define KICK0R *(unsigned int*)(SYS_BASE + 0x038)
#define KICK1R *(unsigned int*)(SYS_BASE + 0x03c)
#define HOST0CFG *(unsigned int*)(SYS_BASE + 0x040)
#define HOST1CFG *(unsigned int*)(SYS_BASE + 0x044)
#define IRAWSTAT *(unsigned int*)(SYS_BASE + 0x0E0)
#define IENSTAT *(unsigned int*)(SYS_BASE + 0x0E4)
#define IENSET *(unsigned int*)(SYS_BASE + 0x0E8)
#define IENCLR *(unsigned int*)(SYS_BASE + 0x0EC)
#define EOI *(unsigned int*)(SYS_BASE + 0x0F0)
#define FLTADDRR *(unsigned int*)(SYS_BASE + 0x0F4)
#define FLTSTAT *(unsigned int*)(SYS_BASE + 0x0F8)
#define MSTPRI0 *(unsigned int*)(SYS_BASE + 0x110)
#define MSTPRI1 *(unsigned int*)(SYS_BASE + 0x114)
#define MSTPRI2 *(unsigned int*)(SYS_BASE + 0x118)
#define PINMUX0 *(unsigned int*)(SYS_BASE + 0x120)
#define PINMUX1 *(unsigned int*)(SYS_BASE + 0x124)
#define PINMUX2 *(unsigned int*)(SYS_BASE + 0x128)
#define PINMUX3 *(unsigned int*)(SYS_BASE + 0x12C)
#define PINMUX4 *(unsigned int*)(SYS_BASE + 0x130)
#define PINMUX5 *(unsigned int*)(SYS_BASE + 0x134)
#define PINMUX6 *(unsigned int*)(SYS_BASE + 0x138)
#define PINMUX7 *(unsigned int*)(SYS_BASE + 0x13C)
#define PINMUX8 *(unsigned int*)(SYS_BASE + 0x140)
#define PINMUX9 *(unsigned int*)(SYS_BASE + 0x144)
#define PINMUX10 *(unsigned int*)(SYS_BASE + 0x148)
#define PINMUX11 *(unsigned int*)(SYS_BASE + 0x14C)
#define PINMUX12 *(unsigned int*)(SYS_BASE + 0x150)
#define PINMUX13 *(unsigned int*)(SYS_BASE + 0x154)
#define PINMUX14 *(unsigned int*)(SYS_BASE + 0x158)
#define PINMUX15 *(unsigned int*)(SYS_BASE + 0x15C)
#define PINMUX16 *(unsigned int*)(SYS_BASE + 0x160)
#define PINMUX17 *(unsigned int*)(SYS_BASE + 0x164)
#define PINMUX18 *(unsigned int*)(SYS_BASE + 0x168)
#define PINMUX19 *(unsigned int*)(SYS_BASE + 0x16C)
#define SUSPSRC *(unsigned int*)(SYS_BASE + 0x170)
#define CHIPSIG *(unsigned int*)(SYS_BASE + 0x174)
#define CHIPSIG_CLR *(unsigned int*)(SYS_BASE + 0x178)
#define CFGCHIP0 *(unsigned int*)(SYS_BASE + 0x17C)
#define CFGCHIP1 *(unsigned int*)(SYS_BASE + 0x180)
#define CFGCHIP2 *(unsigned int*)(SYS_BASE + 0x184)
#define CFGCHIP3 *(unsigned int*)(SYS_BASE + 0x188)
#define CFGCHIP4 *(unsigned int*)(SYS_BASE + 0x18C)
/* ------------------------------------------------------------------------ *
* *
* GPIO Control *
* *
* ------------------------------------------------------------------------ */
#define GPIO_BASE 0x01E26000
#define GPIO_PCR *( volatile Uint32* )( GPIO_BASE + 0x04 )
#define GPIO_BINTEN *( volatile Uint32* )( GPIO_BASE + 0x08 )
// For GPIO[0:31]
#define GPIO_DIR_BASE ( 0x10 ) // Direction Cntl
#define GPIO_OUT_DATA_BASE ( 0x14 ) // Output data
#define GPIO_SET_DATA_BASE ( 0x18 ) // Set data
#define GPIO_CLR_DATA_BASE ( 0x1C ) // Clear data
#define GPIO_IN_DATA_BASE ( 0x20 ) // Input data
#define GPIO_SET_RIS_TRIG_BASE ( 0x24 ) // Set rising edge intr
#define GPIO_CLR_RIS_TRIG_BASE ( 0x28 ) // Clear rising edge intr
#define GPIO_SET_FAL_TRIG_BASE ( 0x2C ) // Set falling edge intr
#define GPIO_CLR_FAL_TRIG_BASE ( 0x30 ) // Clear falling edge intr
#define GPIO_INSTAT_BASE ( 0x34 ) // Intr status
#define GPIO_BASE_OFFSET 0x28
#define GPIO_01_BASE ( GPIO_BASE + 0x10 )
#define GPIO_23_BASE ( GPIO_01_BASE + GPIO_BASE_OFFSET )
#define GPIO_45_BASE ( GPIO_23_BASE + GPIO_BASE_OFFSET )
#define GPIO_6_BASE ( GPIO_45_BASE + GPIO_BASE_OFFSET )
// For GPIO[0:31]
#define GPIO_DIR01 *( volatile Uint32* )( GPIO_BASE + 0x10 )
#define GPIO_OUT_DATA01 *( volatile Uint32* )( GPIO_BASE + 0x14 )
#define GPIO_SET_DATA01 *( volatile Uint32* )( GPIO_BASE + 0x18 )
#define GPIO_CLR_DATA01 *( volatile Uint32* )( GPIO_BASE + 0x1C )
#define GPIO_IN_DATA01 *( volatile Uint32* )( GPIO_BASE + 0x20 )
#define GPIO_SET_RIS_TRIG01 *( volatile Uint32* )( GPIO_BASE + 0x24 )
#define GPIO_CLR_RIS_TRIG01 *( volatile Uint32* )( GPIO_BASE + 0x28 )
#define GPIO_SET_FAL_TRIG01 *( volatile Uint32* )( GPIO_BASE + 0x2C )
#define GPIO_CLR_FAL_TRIG01 *( volatile Uint32* )( GPIO_BASE + 0x30 )
#define GPIO_INSTAT01 *( volatile Uint32* )( GPIO_BASE + 0x34 )
// For GPIO[32:63]
#define GPIO_DIR23 *( volatile Uint32* )( GPIO_BASE + 0x38 )
#define GPIO_OUT_DATA23 *( volatile Uint32* )( GPIO_BASE + 0x3C )
#define GPIO_SET_DATA23 *( volatile Uint32* )( GPIO_BASE + 0x40 )
#define GPIO_CLR_DATA23 *( volatile Uint32* )( GPIO_BASE + 0x44 )
#define GPIO_IN_DATA23 *( volatile Uint32* )( GPIO_BASE + 0x48 )
#define GPIO_SET_RIS_TRIG23 *( volatile Uint32* )( GPIO_BASE + 0x4C )
#define GPIO_CLR_RIS_TRIG23 *( volatile Uint32* )( GPIO_BASE + 0x50 )
#define GPIO_SET_FAL_TRIG23 *( volatile Uint32* )( GPIO_BASE + 0x54 )
#define GPIO_CLR_FAL_TRIG23 *( volatile Uint32* )( GPIO_BASE + 0x58 )
#define GPIO_INSTAT23 *( volatile Uint32* )( GPIO_BASE + 0x5C )
// For GPIO[64:70]
#define GPIO_DIR45 *( volatile Uint32* )( GPIO_BASE + 0x60 )
#define GPIO_OUT_DATA45 *( volatile Uint32* )( GPIO_BASE + 0x64 )
#define GPIO_SET_DATA45 *( volatile Uint32* )( GPIO_BASE + 0x68 )
#define GPIO_CLR_DATA45 *( volatile Uint32* )( GPIO_BASE + 0x6C )
#define GPIO_IN_DATA45 *( volatile Uint32* )( GPIO_BASE + 0x70 )
#define GPIO_SET_RIS_TRIG45 *( volatile Uint32* )( GPIO_BASE + 0x74 )
#define GPIO_CLR_RIS_TRIG45 *( volatile Uint32* )( GPIO_BASE + 0x78 )
#define GPIO_SET_FAL_TRIG45 *( volatile Uint32* )( GPIO_BASE + 0x7C )
#define GPIO_CLR_FAL_TRIG45 *( volatile Uint32* )( GPIO_BASE + 0x80 )
#define GPIO_INSTAT45 *( volatile Uint32* )( GPIO_BASE + 0x84 )
/* ------------------------------------------------------------------------ *
* *
* I2C Controller *
* *
* ------------------------------------------------------------------------ */
#define I2C_BASE 0x01C22000
#define I2C_OAR *( volatile Uint32* )( I2C_BASE + 0x00 )
#define I2C_ICIMR *( volatile Uint32* )( I2C_BASE + 0x04 )
#define I2C_ICSTR *( volatile Uint32* )( I2C_BASE + 0x08 )
#define I2C_ICCLKL *( volatile Uint32* )( I2C_BASE + 0x0C )
#define I2C_ICCLKH *( volatile Uint32* )( I2C_BASE + 0x10 )
#define I2C_ICCNT *( volatile Uint32* )( I2C_BASE + 0x14 )
#define I2C_ICDRR *( volatile Uint32* )( I2C_BASE + 0x18 )
#define I2C_ICSAR *( volatile Uint32* )( I2C_BASE + 0x1C )
#define I2C_ICDXR *( volatile Uint32* )( I2C_BASE + 0x20 )
#define I2C_ICMDR *( volatile Uint32* )( I2C_BASE + 0x24 )
#define I2C_ICIVR *( volatile Uint32* )( I2C_BASE + 0x28 )
#define I2C_ICEMDR *( volatile Uint32* )( I2C_BASE + 0x2C )
#define I2C_ICPSC *( volatile Uint32* )( I2C_BASE + 0x30 )
#define I2C_ICPID1 *( volatile Uint32* )( I2C_BASE + 0x34 )
#define I2C_ICPID2 *( volatile Uint32* )( I2C_BASE + 0x38 )
/* I2C Field Definitions */
#define ICOAR_MASK_7 0x007F
#define ICOAR_MASK_10 0x03FF
#define ICSAR_MASK_7 0x007F
#define ICSAR_MASK_10 0x03FF
#define ICOAR_OADDR 0x007f
#define ICSAR_SADDR 0x0050
#define ICSTR_SDIR 0x4000
#define ICSTR_NACKINT 0x2000
#define ICSTR_BB 0x1000
#define ICSTR_RSFULL 0x0800
#define ICSTR_XSMT 0x0400
#define ICSTR_AAS 0x0200
#define ICSTR_AD0 0x0100
#define ICSTR_SCD 0x0020
#define ICSTR_ICXRDY 0x0010
#define ICSTR_ICRRDY 0x0008
#define ICSTR_ARDY 0x0004
#define ICSTR_NACK 0x0002
#define ICSTR_AL 0x0001
#define ICMDR_NACKMOD 0x8000
#define ICMDR_FREE 0x4000
#define ICMDR_STT 0x2000
#define ICMDR_IDLEEN 0x1000
#define ICMDR_STP 0x0800
#define ICMDR_MST 0x0400
#define ICMDR_TRX 0x0200
#define ICMDR_XA 0x0100
#define ICMDR_RM 0x0080
#define ICMDR_DLB 0x0040
#define ICMDR_IRS 0x0020
#define ICMDR_STB 0x0010
#define ICMDR_FDF 0x0008
#define ICMDR_BC_MASK 0x0007
/* ------------------------------------------------------------------------ *
* *
* INTC controller *
* Controls the Interrupts *
* *
* ------------------------------------------------------------------------ */
#define INTC_BASE 0xFFFE0000
#define INTC_FIQ0 *( volatile Uint32* )( INTC_BASE + 0x00 )
#define INTC_FIQ1 *( volatile Uint32* )( INTC_BASE + 0x04 )
#define INTC_IRQ0 *( volatile Uint32* )( INTC_BASE + 0x08 )
#define INTC_IRQ1 *( volatile Uint32* )( INTC_BASE + 0x0C )
#define INTC_FIQENTRY *( volatile Uint32* )( INTC_BASE + 0x10 )
#define INTC_IRQENTRY *( volatile Uint32* )( INTC_BASE + 0x14 )
#define INTC_EINT0 *( volatile Uint32* )( INTC_BASE + 0x18 )
#define INTC_EINT1 *( volatile Uint32* )( INTC_BASE + 0x1C )
#define INTC_INTCTL *( volatile Uint32* )( INTC_BASE + 0x20 )
#define INTC_EABASE *( volatile Uint32* )( INTC_BASE + 0x24 )
#define INTC_INTPRI0 *( volatile Uint32* )( INTC_BASE + 0x30 )
#define INTC_INTPRI1 *( volatile Uint32* )( INTC_BASE + 0x34 )
#define INTC_INTPRI2 *( volatile Uint32* )( INTC_BASE + 0x38 )
#define INTC_INTPRI3 *( volatile Uint32* )( INTC_BASE + 0x3C )
#define INTC_INTPRI4 *( volatile Uint32* )( INTC_BASE + 0x40 )
#define INTC_INTPRI5 *( volatile Uint32* )( INTC_BASE + 0x44 )
#define INTC_INTPRI6 *( volatile Uint32* )( INTC_BASE + 0x48 )
#define INTC_INTPRI7 *( volatile Uint32* )( INTC_BASE + 0x4C )
/* ------------------------------------------------------------------------ *
* *
* PLL0 Controller *
* Generates DSP clocks *
* *
* ------------------------------------------------------------------------ */
#define PLL0_BASE 0x01C11000 /*SYSTEM PLL BASE ADDRESS*/
#define PLL0_PID *(unsigned int*) (PLL0_BASE + 0x00) /*PID*/
#define PLL0_FUSERR *(unsigned int*) (PLL0_BASE + 0xE0) /*x*FuseFarm Error Reg*/
#define PLL0_RSTYPE *(unsigned int*) (PLL0_BASE + 0xE4) /*Reset Type status Reg*/
#define PLL0_PLLCTL *(unsigned int*) (PLL0_BASE + 0x100) /*PLL Control Register*/
//#define PLL0_OCSEL *(unsigned int*) (PLL0_BASE + 0x104) /*OBSCLK Select Register*/
#define PLL0_SECCTL *(unsigned int*) (PLL0_BASE + 0x108) /*PLL Secondary Control Register*/
#define PLL0_PLLM *(unsigned int*) (PLL0_BASE + 0x110) /*PLL Multiplier*/
#define PLL0_PREDIV *(unsigned int*) (PLL0_BASE + 0x114) /*Pre divider*/
#define PLL0_PLLDIV1 *(unsigned int*) (PLL0_BASE + 0x118) /*Diveder-1*/
#define PLL0_PLLDIV2 *(unsigned int*) (PLL0_BASE + 0x11C) /*Diveder-2*/
#define PLL0_PLLDIV3 *(unsigned int*) (PLL0_BASE + 0x120) /*Diveder-3*/
//#define PLL0_OSCDIV1 *(unsigned int*) (PLL0_BASE + 0x124) /*Oscilator Divider*/
#define PLL0_POSTDIV *(unsigned int*) (PLL0_BASE + 0x128) /*Post Divider*/
#define PLL0_BPDIV *(unsigned int*) (PLL0_BASE + 0x12C) /*Bypass Divider*/
#define PLL0_WAKEUP *(unsigned int*) (PLL0_BASE + 0x130) /*Wakeup Reg*/
#define PLL0_PLLCMD *(unsigned int*) (PLL0_BASE + 0x138) /*Command Reg*/
#define PLL0_PLLSTAT *(unsigned int*) (PLL0_BASE + 0x13C) /*Status Reg*/
#define PLL0_ALNCTL *(unsigned int*) (PLL0_BASE + 0x140) /*Clock Align Control Reg*/
#define PLL0_DCHANGE *(unsigned int*) (PLL0_BASE + 0x144) /*PLLDIV Ratio Chnage status*/
#define PLL0_CKEN *(unsigned int*) (PLL0_BASE + 0x148) /*Clock Enable Reg*/
#define PLL0_CKSTAT *(unsigned int*) (PLL0_BASE + 0x14C) /*Clock Status Reg*/
#define PLL0_SYSTAT *(unsigned int*) (PLL0_BASE + 0x150) /*Sysclk status reg*/
#define PLL0_PLLDIV4 *(unsigned int*) (PLL0_BASE + 0x160) /*Divider 4*/
#define PLL0_PLLDIV5 *(unsigned int*) (PLL0_BASE + 0x164) /*Divider 5*/
#define PLL0_PLLDIV6 *(unsigned int*) (PLL0_BASE + 0x168) /*Divider 6*/
#define PLL0_PLLDIV7 *(unsigned int*) (PLL0_BASE + 0x16C) /*Divider 7*/
#define PLL0_PLLDIV8 *(unsigned int*) (PLL0_BASE + 0x170) /*Divider 8*/
#define PLL0_PLLDIV9 *(unsigned int*) (PLL0_BASE + 0x174) /*Divider 9*/
#define PLL0_PLLDIV10 *(unsigned int*) (PLL0_BASE + 0x178) /*Divider 10*/
#define PLL0_PLLDIV11 *(unsigned int*) (PLL0_BASE + 0x17C) /*Divider 11*/
#define PLL0_PLLDIV12 *(unsigned int*) (PLL0_BASE + 0x180) /*Divider 12*/
#define PLL0_PLLDIV13 *(unsigned int*) (PLL0_BASE + 0x184) /*Divider 13*/
#define PLL0_PLLDIV14 *(unsigned int*) (PLL0_BASE + 0x188) /*Divider 14*/
#define PLL0_PLLDIV15 *(unsigned int*) (PLL0_BASE + 0x18C) /*Divider 15*/
#define PLL0_PLLDIV16 *(unsigned int*) (PLL0_BASE + 0x190) /*Divider 16*/
#define PLLEN_MUX_SWITCH 4
#define PLL_LOCK_TIME_CNT 2400
/* ------------------------------------------------------------------------ *
* *
* Timer Controller *
* *
* ------------------------------------------------------------------------ */
#define TIMER0_BASE 0x01C20000
#define TIMER0_EMUMGT *( volatile Uint32* )( TIMER0_BASE + 0x04 )
#define TIMER0_TIM12 *( volatile Uint32* )( TIMER0_BASE + 0x10 )
#define TIMER0_TIM34 *( volatile Uint32* )( TIMER0_BASE + 0x14 )
#define TIMER0_PRD12 *( volatile Uint32* )( TIMER0_BASE + 0x18 )
#define TIMER0_PRD34 *( volatile Uint32* )( TIMER0_BASE + 0x1C )
#define TIMER0_TRC *( volatile Uint32* )( TIMER0_BASE + 0x20 )
#define TIMER0_TGCR *( volatile Uint32* )( TIMER0_BASE + 0x24 )
#define TIMER1_BASE 0x01C21000
#define TIMER1_EMUMGT *( volatile Uint32* )( TIMER1_BASE + 0x04 )
#define TIMER1_TIM12 *( volatile Uint32* )( TIMER1_BASE + 0x10 )
#define TIMER1_TIM34 *( volatile Uint32* )( TIMER1_BASE + 0x14 )
#define TIMER1_PRD12 *( volatile Uint32* )( TIMER1_BASE + 0x18 )
#define TIMER1_PRD34 *( volatile Uint32* )( TIMER1_BASE + 0x1C )
#define TIMER1_TRC *( volatile Uint32* )( TIMER1_BASE + 0x20 )
#define TIMER1_TGCR *( volatile Uint32* )( TIMER1_BASE + 0x24 )
#define TIMER_EMUMGT ( 0x04 )
#define TIMER_TIM12 ( 0x10 )
#define TIMER_TIM34 ( 0x14 )
#define TIMER_PRD12 ( 0x18 )
#define TIMER_PRD34 ( 0x1C )
#define TIMER_TRC ( 0x20 )
#define TIMER_TGCR ( 0x24 )
/* ------------------------------------------------------------------------ *
* *
* UART Controller *
* *
* ------------------------------------------------------------------------ */
#define UART0_BASE 0x01C42000
#define UART0_RBR *( volatile Uint32* )( UART0_BASE + 0x00 )
#define UART0_THR *( volatile Uint32* )( UART0_BASE + 0x00 )
#define UART0_IER *( volatile Uint32* )( UART0_BASE + 0x04 )
#define UART0_IIR *( volatile Uint32* )( UART0_BASE + 0x08 )
#define UART0_FCR *( volatile Uint32* )( UART0_BASE + 0x08 )
#define UART0_LCR *( volatile Uint32* )( UART0_BASE + 0x0C )
#define UART0_MCR *( volatile Uint32* )( UART0_BASE + 0x10 )
#define UART0_LSR *( volatile Uint32* )( UART0_BASE + 0x14 )
#define UART0_DLL *( volatile Uint32* )( UART0_BASE + 0x20 )
#define UART0_DLH *( volatile Uint32* )( UART0_BASE + 0x24 )
#define UART0_PID1 *( volatile Uint32* )( UART0_BASE + 0x28 )
#define UART0_PID2 *( volatile Uint32* )( UART0_BASE + 0x2C )
#define UART0_PWREMU_MGMT *( volatile Uint32* )( UART0_BASE + 0x30 )
#define UART1_BASE 0x01D0C000
#define UART1_RBR *( volatile Uint32* )( UART1_BASE + 0x00 )
#define UART1_THR *( volatile Uint32* )( UART1_BASE + 0x00 )
#define UART1_IER *( volatile Uint32* )( UART1_BASE + 0x04 )
#define UART1_IIR *( volatile Uint32* )( UART1_BASE + 0x08 )
#define UART1_FCR *( volatile Uint32* )( UART1_BASE + 0x08 )
#define UART1_LCR *( volatile Uint32* )( UART1_BASE + 0x0C )
#define UART1_MCR *( volatile Uint32* )( UART1_BASE + 0x10 )
#define UART1_LSR *( volatile Uint32* )( UART1_BASE + 0x14 )
#define UART1_DLL *( volatile Uint32* )( UART1_BASE + 0x20 )
#define UART1_DLH *( volatile Uint32* )( UART1_BASE + 0x24 )
#define UART1_PID1 *( volatile Uint32* )( UART1_BASE + 0x28 )
#define UART1_PID2 *( volatile Uint32* )( UART1_BASE + 0x2C )
#define UART1_PWREMU_MGMT *( volatile Uint32* )( UART1_BASE + 0x30 )
#define UART2_BASE 0x01D0D000
#define UART2_RBR *( volatile Uint32* )( UART2_BASE + 0x00 )
#define UART2_THR *( volatile Uint32* )( UART2_BASE + 0x00 )
#define UART2_IER *( volatile Uint32* )( UART2_BASE + 0x04 )
#define UART2_IIR *( volatile Uint32* )( UART2_BASE + 0x08 )
#define UART2_FCR *( volatile Uint32* )( UART2_BASE + 0x08 )
#define UART2_LCR *( volatile Uint32* )( UART2_BASE + 0x0C )
#define UART2_MCR *( volatile Uint32* )( UART2_BASE + 0x10 )
#define UART2_LSR *( volatile Uint32* )( UART2_BASE + 0x14 )
#define UART2_DLL *( volatile Uint32* )( UART2_BASE + 0x20 )
#define UART2_DLH *( volatile Uint32* )( UART2_BASE + 0x24 )
#define UART2_PID1 *( volatile Uint32* )( UART2_BASE + 0x28 )
#define UART2_PID2 *( volatile Uint32* )( UART2_BASE + 0x2C )
#define UART2_PWREMU_MGMT *( volatile Uint32* )( UART2_BASE + 0x30 )
#define UART_RBR ( 0x00 )
#define UART_THR ( 0x00 )
#define UART_IER ( 0x04 )
#define UART_IIR ( 0x08 )
#define UART_FCR ( 0x08 )
#define UART_LCR ( 0x0C )
#define UART_MCR ( 0x10 )
#define UART_LSR ( 0x14 )
#define UART_DLL ( 0x20 )
#define UART_DLH ( 0x24 )
#define UART_PID1 ( 0x28 )
#define UART_PID2 ( 0x2C )
#define UART_PWREMU_MGMT ( 0x30 )
/* ------------------------------------------------------------------------ *
* *
* PSC Module Related Registers *
* *
* ------------------------------------------------------------------------ */
#define PSC0_BASE 0x01C10000
#define PSC1_BASE 0x01E27000
#define PSC0_MDCTL (PSC0_BASE+0xA00)
#define PSC0_MDSTAT (PSC0_BASE+0x800)
#define PSC0_PTCMD *(unsigned int*) (PSC0_BASE + 0x120)
#define PSC0_PTSTAT *(unsigned int*) (PSC0_BASE + 0x128)
#define PSC1_MDCTL (PSC1_BASE+0xA00)
#define PSC1_MDSTAT (PSC1_BASE+0x800)
#define PSC1_PTCMD *(unsigned int*) (PSC1_BASE + 0x120)
#define PSC1_PTSTAT *(unsigned int*) (PSC1_BASE + 0x128)
/* ------------------------------------------------------------------------ *
* Prototypes *
* ------------------------------------------------------------------------ */
void P2_Config_init ( void );
void P2_PLL_init ( void );
void P2_setup_PLL ( Uint8 CLK, Uint8 MLP );
void P2_PSC0_init ( Uint32 PD, Uint32 LPSC_num );
void P2_PSC1_init ( Uint32 PD, Uint32 LPSC_num );
void P2_Pwr_init ( void );
void P2_board_init ( void );
void P2_GPIO_init ( void );
void P2_Uart_init ( Uint8 Port, Uint32 Baudrate );
void P2_Uart_putchar ( Uint8 Port, Uint8 Data );
Int8 P2_Uart_getchar ( Uint8 Port );
void P2_Uart_send_data ( Uint8 Port, Uint8 *BufferPtr, Uint16 Length );
void P2_Int_init ( Uint8 Port, Uint8 Port_num, Uint8 Port_edge ,Uint8 Int_num);
void P2_SPI_init ( void );
void P2_I2C_init ( void );
void P2_DMA_init ( void );
void P2_SDRAM_init ( void );
void P2_TIMER_init ( Uint8 Tmr_num, Uint32 delay, Uint8 Int_num);
void P2_wait ( Uint32 delay );
#endif
/*----dsp.c----*/
/*
*********************************************************************************************************
* P2 MAIN FUNCTIONS
*
* (c) Copyright 2010; Havelsan A.S.; Ankara, Turkiye
*
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
*
*
* Texas Instruments TMX320C6745PTP3
* on the
*
* Filename : pams_dsp.c
* Version : V1.00
*********************************************************************************************************
*/
#include "bsp.h"
Int16 GPIO_setDirection( Uint16 number, Uint8 direction )
{
Uint32 bank_id = ( number >> 5 );
Uint32 pin_id = ( 1 << ( number & 0x1F ) );
Uint32* gpio_dir = ( Uint32* )( GPIO_BASE + GPIO_DIR_BASE + ( bank_id * GPIO_BASE_OFFSET ) );
if ( ( direction & 1 ) == direction )
*gpio_dir &= ~( pin_id ); // Set to OUTPUT
else
*gpio_dir |= ( pin_id ); // Set to INPUT
return 0;
}
void main(void)
{
P2_Config_init();
P2_Pwr_init();
GPIO_setDirection(1,0);
GPIO_setDirection(2,0);
GPIO_setDirection(3,0);
GPIO_setDirection(4,0);
P2_Uart_init(2,921600);
while(1)
{
GPIO_OUT_DATA01 |=0x0000000E;
for(i=0;i<50000;i++)
{
a=1;
}
GPIO_OUT_DATA01 &=~(0x0000000E);
for(i=0;i<50000;i++)
{
a=1;
}
}
}
/*---- .cmd file----*/
-c
-heap 0x1000
-stack 0x1000
MEMORY
{
L1D: o = 00F00000h l = 00008000h
L1P: o = 00E00000h l = 00008000h
L2: o = 00800000h l = 00040000h
}
/* .vecs sections is added here to avoid compiler warning that the .vecs section
* defined in the asm file is not mapped to memory section
*/
SECTIONS
{
.text > L2
.stack > L2
.bss > L2
.cinit > L2
.cio > L2
.const > L2
.sysmem > L2
.far > L2
.switch > L2
.vecs > L2
}
