OSPI DDR Read Data

Hello Yajuan,

Please indicate what PROCESSOR you are using.

Thank you,

~Leonard 

Hi Leonard 

I am using DRA828.

Thanks.

1) In DDR mode, you must read back an even number of bytes.  If you only want one byte, as is the case with a single byte register, read two bytes, and disregard the upper byte.

2)  What frequency are you using, and is PHY enabled?

1.Why does the MIRON flash DDR mode of the development board read two bytes without ignoring the high byte operation? Can you point me to the operation?

2.I used the 133MHZ clock frequency and turned on the PHY, so after reading the flash ID 128 times through the PHY, the delay parameters in the PHY will be continuously adjusted to read the correct flash ID. However, because CYPRESS's volatile register and memory arry need to set different dummy cycles, and the delay parameter adjustment of phy is adjusted according to the flash ID, which is equivalent to adjusting the dummy clcle of accessing the volatile register, without adjusting the memory's dummy cycle. So now even if I read the correct flash ID, I cannot read the correct memory data.

Hi, Zack,

I have gone through the OSPI_Flash_TestApp demo in SDK, and found that no matter ospi_cfg.dtrEnable = true or false, Nor_ospiReadId() is call to read 3 bytes of OSPI chip ID. There is no difference for DDR and SDR.

I think this causes customer engineer's confusing.

Please help to explain in more details and point out the process for odd byte data process in SDK.

Thanks.

Hi, Zack,

I did some more test with Micron OSPI on J7 EVM, and got below result. Please help to analysis and share your comments. Thanks.

I did some modification in Nor_ospiOpen() and CSL_ospuConfigPhy() to disable data training and set to a fixed TX/RX values found in table 5-111 in DM. Then tried to read ID of Micron OSPI chip. Below is data gotten from OSPI_FLASH_RD_DATA_LOWER_REG  and OSPI_FLASH_RD_DATA_UPPER_REG with different rxLen set in NOR_ospiCmdRead().

This test is based on OSPI_Flash_TestApp, other settings were not modified.

Why the lower 2 bytes gotten in OSPI_FLASH_RD_DATA_LOWER_REG were always 0x0000?

Thanks.

DDR mode without data training is limited to very low speeds.  It is possible you are operating at too high of a speed.  But Yajuan is using data training.

I can't comment on what the SDK does, only that the controller needs an even number of samples in DDR mode.

" However, because CYPRESS's volatile register and memory arry need to set different dummy cycles, and the delay parameter adjustment of phy is adjusted according to the flash ID, which is equivalent to adjusting the dummy clcle of accessing the volatile register, without adjusting the memory's dummy cycle."

I don't really understand this statement from Yajuan, especially the bold part.

Hi, Zack,

Thanks for the response.

I redo the test with data training enabled. HW: J7 EVM. SW: psdk_rtos_auto_j7_07_00_00_11. Just add Nor_ospiReadId() after calibrating PHY.

During the test, I found that when read odd number of byte, the data gotten from OSPI_FLASH_RD_DATA register is correct. But when read even number of byte, the data gotten from OSPI_FLASH_RD_DATA register is different on each read. Please help to check if anything wrong in my test, Thanks.

Hi, Zack,

From above test, I got the result that

1. If try to read odd number(n) of byte in DDR mode, n+1 bytes were read back into OSPI_FLASH_RD_DATA register, the lower n bytes from these n+1 bytes are the correct content expected.

2. If try to read even number of byte in DDR mode, the contents gotten in OSPI_FLASH_RD_DATA register differed in each read.

Would you please help to check whether you can reproduce the same issue with J7 EVM and psdk_rtos_auto_j7_07_00_00_11, and help to check if anything wrong in my test, and guide the way to read even number of byte in DDR mode.

Thanks.

Hi Fan,

The PDK OSPI driver API expects the caller to follow the requirement for odd/even number of bytes based SDR or DDR mode.

The driver does NOT take care of this requirement for the application.

Regards,
Stanley

Hi, Stanley

Thanks for your reply.

Based on my understanding, even number of bytes is transferred in DDR mode. If odd number(n) of bytes is expected, (n+1) bytes is read out and caller can just ignore the highest bytes to get the expected odd number of bytes. And my test result above is consistent with my understanding.

For even number of bytes read operation, it should be more simple because the ignoring is unnecessary. But the readout content in OSPI_FLASH_RD_DATA register differed in each read.

Would you help to guide the way to read even number of ID using NOR_ospiCmdRead() API.

Thanks.

Hi, Stanley,

Would you help to check if anything wrong in my operation while reading 2/4 bytes of OSPI chip ID?

Thanks.

Hi Fan,

Fan_Zhang said:

Would you help to check if anything wrong in my operation while reading 2/4 bytes of OSPI chip ID?

Does this problem still need attention? Can you please post back on this thread with what actions are needed?

Regards

Karthik

Hi, Karthik,

Yes, this issue is still open.

Please help to check if anything wrong in the operations to read 2/4 bytes of OSPI chip ID. If the same phenomenon in your side with J7 EVM.

Thanks.