TMS320C6748: C6748 QDMA completion status check

Peter Hong

Part Number: TMS320C6748

I have set up QDMA to read a 16-bit port 16 times and transfer the readings to memory. The transfer operation works as expected. The completion of transfer is polled by checking the IPR, rather than using interrupt.

I observed, however, that timing of other interrupts, seemingly interrupt latency is affected by QDMA. I verified this by compiling in and out the QDMA code. Is this expected behavior?

I perform the following before initiating QDMA:

//clear event missed status bit
HWREG(QEMCR) = 0x00000001;
//clear interrupt status
HWREG(ICR) = 0x00000001;
//clear interrupt enable
HWREG(IECR) = 0x00000001;
// trigger DMA
data_PaRAM.opt = 0x0010000C; //TCINTEN=1, STATIC=1, AB synchronization

over 5 years ago

0 Sahin Okur over 5 years ago

TI__Mastermind 27355 points

Hello,

Is the DMA/CPU accessing L2? I wonder if you are being impacted by Advisory 2.3.1 in the Errata.

Also, you are auto-triggering the QDMA transfer, correct? What other interrupts are going in the system? And do you know roughly how much the interrupt latency is affected by the QDMA?

Regards,
Sahin

0 Peter Hong over 5 years ago in reply to Sahin Okur

Intellectual 966 points

No L2 involved in memory transfer.

There are two interrupts: 1. external and periodic, 2. timer generated and occurs more frequently than #1, typically 100 us to tens of milliseconds from timer setup and occurs in series, one after another.

When QDMA is disabled, timing measurements between interrupts are pretty much dead on. When QDMA is disabled, timing measurements are late by 2 to 6 microseconds.

QDMA is used in polled mode. IPR bit checked.

0 Peter Hong over 5 years ago in reply to Peter Hong

Intellectual 966 points

Bump

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TMS320C6748: C6748 QDMA completion status check