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TMS320C5517: Using McBSP-DMA to bring in byte data, seem to need 4x RAM to do so?

Part Number: TMS320C5517


I am having a problem using McBSP-DMA on the 5517.  I can get data
to our RAM buffer, but I have to do weird things with DMA frame length
and RAM buffer element size to do so.

I am using the McBSP to bring in 9 bytes at a time per timeslot,
triggered on a per-timeslot basis using external clock FSR.

I set the McBSP word length RCRL:RWDLEN1 to be 8 bits, and frame length
to be 9 words by setting RCRL:RFRLEN1 = 8.

Our data chunk consists of 16 timeslots  It is this chunk that
we are DMA'ing to RAM (in this case internal SARAM).  

So I thought my DMA transfer size would be 9 bytes/timeslot * 16 timeslots = 144.

I have set the DMA transfer size to be 144 (DMA3:DMACH0TRCL) with interrupt
enabled, and I get the interrupt.  The DMA destination and source addresses
are all OK.  DMA burst mode is set to 0 = 1 double word.

But when I look at the receive RAM buffer, a word array 144 elements
in size, I'm not seeing what I expect.  I only see expected data once in a
while as I hit the DMA ISR breakpoint.  My Uint16 rcvBuff[144] is not working.

Here's what "fixed" it - if I change the DMA length (DMA3:DMACH0TRCL)
to be 576, 4 times my 144 bytes in, and change the element size of my
receive buffer to be 32 bits, ie Uint32 rcvBuff[144], I see my data.

I see the Nth byte of my expected data in the Nth element of my receive
buffer.  So for example if my data is sequential I'll see this:


 McBSP in        data       DMA destination receive buffer
first byte         0         rcvBuff[0]    = 0x0000000
second byte        1         rcvBuff[1]    = 0x0000001
third byte         2         rcvBuff[2]    = 0x0000002
 ...
144th byte       143         rcvBuff[143]  = 0x000008F  (143d)
 
The data is getting through to RAM, just not how I want or expect.  
--I have to make the DMA length 4 times the size of the data
--I have to make the receiving buffer elements 4 bytes in size.

I figure I have something misconfigured, just not sure what.

I'd like to have my receive buffer to be a word array: Uint16 rcvBuff[144]
and I'd like my DMA length to be 144.  Or know why not.

Can anyone shed any light?

Thanks,

Steve


  • Hi, Steve,

    Isn't the length in DMA0TRCL be configured at 4 times of that as stated in the register description: "Value 0004h to FFFCh: These bits specify the number of double words (specified in bytes) to be transferred in multiples of (4 x 2 BURSTMODE) bytes"?

    Rex

  • Rex,

    I read that description, and that's what prompted me to try allocating 4x the size.  I thought some sort of packing that can happen, ie bytes in McBSP = words out DMA.  Apparently not, at least for my use-case? 

    To make sure I really understand - for each 8-bit data element coming in the McBSP, I must allocate 32 bits of DMA-destination RAM to receive it.  True?

    Thanks,

    Steve

  • Hi, Steve,

    You are in the right direction,  Keep in mind that the DMA always copies 32-bits.

    Rex

  • Thanks for following up Rex.  Much appreciated!

    Is the same logic true for the transmit?  32bit element in RAM (low 8 bits real data) --> DMA -->  8bit element Tx out the McBSP ?

    I have been pointing the DMA at an array of 144 32-bit elements to send 144 8-bit elements out the McBSP.  I'm not looking to do any data packing using frame sync ignore.

    I ask because I used 32-bit array elements as well as 16-bit array elements for my Tx source RAM array, both with desired data in the low 8 bits, and got the same results out on the wire.

    Thanks,

    Steve

  • Hi, Steve,

    Sorry for the slow response. I'll have to check internally on your question.

    Rex

  • Hi Steve,

    By default the McBSP will work as Transmit Frame Ignore bit (XFIG) set to disable, therefore every frame will trigger a DMA event, then a DMA copy. As Rex mentioned before the DMA is 32 bit transfer, so even you only have 8 bit data in the register, it will copy 32 bit into the memory buffer. If you want to use the "packed mode", you will need to set the Transmit Frame Ignore bit to 1. The same thing is true for the receiving, of course the RFIG needs to be set to 1.

    If you choose to use the "unpacked mode", then you have to allocate x4 bigger buffer.

    Ming