AM5748: NAND ECC Mapping

Mike Chu

Part Number: AM5748

We're trying to run a Micron MT29F16G08AJADAWP on a custom AM5748, and we're confused as to how to configure the am57xx_evm.h file, especially for ECC. The page size for the Micron device is 2048 bytes, with OOB size 64 bytes, so the ECC algorithm we'd want to use would be BCH8, correct? Would this mean we set CONFIG_SYS_NAND_ECCBYTES to 14? How do we decide on CONFIG_SYS_NAND_ECCPOS?

Thanks!

over 5 years ago

0 Keerthy J over 5 years ago

TI__Guru**** 164490 points

Hello Mike,

I will be consulting experts on this and get back to you in couple of days.

- Keerthy

0 Vishal Mahaveer over 5 years ago in reply to Keerthy J

TI__Mastermind 33410 points

Hi Mike,

For page size 2048 bytes with OOB size 64 bytes, BCH8 is correct and CONFIG_SYS_NAND_ECCBYTES should be set to 14
https://processors.wiki.ti.com/index.php/Raw_NAND_ECC#Is_it_possible_to_use_any_ECC_algorithm_for_any_NAND.3F

For CONFIG_SYS_NAND_ECCPOS use the below for BCH8 (reference taken from include/configs/dra7xx_evm.h)

#define CONFIG_SYS_NAND_ECCPOS \ {
2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
34, 35, 36, 37, 38, 39, 40, 41, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }

Regards,
Vishal

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AM5748: NAND ECC Mapping