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OMAP3530 to DM3730 Migration - package considerations

Mahdi Olfat
Prodigy 60 points

Other Parts Discussed in Thread: DM3730, OMAP3530

Hi,

We are trying to migrate from the OMAP3530 to DM3730. The OMAP3530 currently being used in our product uses POP (Package-on-Package) for LPDDR. But, for the DM3730 we would like to not do that (not use POP) and put the LPDDR on the PCB itself. However, it shows on the datasheet for the DM3730 that the only package that would let us do that is the CUS package with 423-pins. The POP packages (CBP and CBC) have 515 pins.

The question is:

  • if we are migrating from an OMAP3530 which uses POP for LPDDR to a DM3730 which would use non-POP LPDDR, is everything else going to stay the same? Or due to less number of pins, pin-muxing is extensive on the CUS package and we would have to do major software changes for other interfaces?
  • How different are the pin-muxing on the different packages of the DM3730? 
  • Why are there way more pins on the CBP and CBC packages (NC pins?)?

Your help is much appreciated.

-Mahdi

  • 0
    TI__Expert 6735 points

    Mahdi:

    The Pin Mux Utility is useful for comparing package differences and pin muxing options.  You can download this tool here:

    http://focus.ti.com/docs/toolsw/folders/print/pinmuxtool.html

    User's Guide wiki page is here:

    http://processors.wiki.ti.com/index.php/Pin_Mux_Utility_for_ARM_MPU_Processors

     

    The CBP package supports POP memory.  It has the GPMC interface going to both top and bottom balls.  The SDRC interface

    goes to the top.  The CBP package has 515 balls on the bottom and 168 balls on top.   The CBP package has a lot of NC balls.

     

    The CUS package is non-POP.   It has the SDRC interface going to the bottom.  The CUS package has 423 balls and there are

    very few NC balls.   

     

    The pin-muxing at the silicon die level is independent of the package.  For the CUS package, however, you can see in the Pin Mux Utility

    tool that there are about 20 pin-muxable signals that are not balled out on the CUS package.  These include some interfaces that are muxed

    out to multiple locations, some GPMC signals and some GPIOs.

     

    Please see the OMAP35xx to AM37xx migration guide for more details.

    http://processors.wiki.ti.com/index.php/OMAP35x_To_AM37x_Hardware_Migration_Guide

    Regards,

    Michael T

    PS: Please mark this post as answered via the Verify Answer button below if you think it answers your question.  Thanks!

     

  • 0 in reply to Michael T
    Prodigy 60 points

    Thanks for your reply.

    I have tried to see if we are using the 20 pin-muxable signals that are not balled out on the CUS package (as you mentioned.).

    The GPIOs should not be a problem. However, for the GPMC interface, we will be using NAND Flash. On the Pin Mux Utility program, all the GPMC signals seem to be available except that out of the 8 chip-select and wait pins for GPMC (ncs[7:0] and wait[7:0]), ncs[1], ncs[2], wait[1] and wait[2] are NOT available.


    Please confirm that we will be able to use NAND Flash given that the said pins are not available.

     

    Thanks,

    Mahdi

  • 0 in reply to Mahdi Olfat
    TI__Expert 6735 points

    Mahdi:

    In order to answer your question I would need to know exactly what NAND device you will be using, which chip selects you plan to use, etc.

    Regards,

    Michael T

  • 0 in reply to Michael T
    Prodigy 60 points

    Hi Micheal,

     

    It's a 2Gb NAND. I would like to make sure that one of the available chip-selects (out of the 6) is the boot chip select pin. I think overall we would need 2 chip selects for 2Gb NAND.

     

    Thanks,

    Mahdi

  • 0 in reply to Mahdi Olfat
    TI__Expert 6735 points

    Mahdi:

    Only a single chip select is needed with a 2Gbit (256MB) NAND device.

    On DM3730,  the GPMC chip select space is specified as 256 MB max for CS0 & CS1 and 128 MB max for CS2-CS7.

    But these limits do not apply to NAND devices, since they are not directly memory mapped.