Hi,
software version: ti_vision_sdk_v3.5
I just switching the uart2 driver from m4 core to A15. My m4 uart2 driver is fine, pls refer code below.
#include "apa_uart_drv.h"
#include <ti/csl/hw_types.h>
#include <ti/csl/soc.h>
#include <ti/csl/cslr_synctimer.h>
#include <ti/csl/src/ip/uart/V1/hw_uart.h>
#include <ti/csl/src/ip/uart/V1/uart.h>
#include <ti/csl/csl_uart.h>
#include <ti/csl/arch/csl_arch.h>
#include <ti/drv/vps/include/common/bsp_utils.h>
#include <ti/drv/stw_lld/platform/irq_xbar_interrupt_ids.h>
#include <ti/sysbios/family/shared/vayu/IntXbar.h>
#include <src/rtos/utils_common/include/utils.h>
#include "include/link_api/system.h"
#include "include/link_api/system_common.h"
//#include <ti/csl/example/utils/uart_console/inc/uartConfig.h>
extern Int32 Vps_printf(const char *format, ...);
/******************************************************************************
** INTERNAL MACRO DEFINITIONS
******************************************************************************/
#define XBAR_CPU (CSL_XBAR_IRQ_CPU_ID_IPU2)
#if defined (SOC_TDA2XX) || defined (SOC_TDA2PX) || defined (SOC_TDA2EX)
//#define UART_INT_ID (44U)
//#define XBAR_INST (CSL_XBAR_INST_IPU2_IRQ_44)
//#define XBAR_INTR_SOURCE (CSL_XBAR_UART5_IRQ)
#elif defined (SOC_TDA3XX)
#define UART_INT_ID (45U)
#define XBAR_INST (CSL_XBAR_INST_IPU1_IRQ_45)
#define XBAR_INTR_SOURCE (CSL_XBAR_UART3_IRQ)
#endif
//#define UART5_INTR_NUM 68
//#define UART5_INTR_NUM CSL_XBAR_INST_IPU1_IRQ_45
//#define UART5_INTR_NUM CSL_XBAR_INST_IPU2_IRQ_69
//#define UART5_INTR_SRC CSL_XBAR_UART5_IRQ
#define UART2_INTR_NUM CSL_XBAR_INST_IPU2_IRQ_69
#define UART2_INTR_SRC CSL_XBAR_UART2_IRQ
/******************************************************************************
** INTERNAL FUNCTION PROTOTYPES
******************************************************************************/
static void APA_UART_setPinmuxRegs(uint32_t baseAddrOffset, uint32_t ioPinCfg);
static void APA_UART_InstInit(void);
static void APA_UART_IntEnable(uint32_t base);
static void APA_UART_INTCConfig(void);
static void APA_UART_FIFOConfigure(uint32_t base);
static void APA_UART_BaudRateSet(uint32_t base);
/******************************************************************************
** GLOBAL VARIABLE DEFINITIONS
******************************************************************************/
const uint32_t ruw_apaUartBasePtrs[APA_SOC_MCU_UART_TOTAL] = APA_SOC_MCU_UART_BASE_PTRS;
const APA_SOC_MCU_uart_t rs_apaSocMcuUart[APA_SOC_MCU_UART_TOTAL] = APA_SOC_MCU_UART_INFO;
uint32_t ruw_apaSocMcuUartBase;
BspOsal_IntrHandle gUtils_tempHwiHandle;
/******************************************************************************
** FUNCTION DEFINITIONS
******************************************************************************/
static void APA_UART_setPinmuxRegs(uint32_t baseAddrOffset, uint32_t ioPinCfg)
{
uint32_t tmpRegVal;
/* Unlock MMR_5 for pin muxing */
HW_WR_REG32(
SOC_CTRL_MODULE_CORE_CORE_REGISTERS_BASE +
CTRL_CORE_MMR_LOCK_5,
CTRL_CORE_MMR_LOCK_5_MMR_LOCK_5_TOUNLOCK);
tmpRegVal = HW_RD_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE + baseAddrOffset);
tmpRegVal &= ~(0xF000FU);
tmpRegVal |= (ioPinCfg & 0xF000FU);
HW_WR_REG32((SOC_CORE_PAD_IO_REGISTERS_BASE + baseAddrOffset), tmpRegVal);
/* Lock MMR_5 for pin muxing */
HW_WR_REG32(
SOC_CTRL_MODULE_CORE_CORE_REGISTERS_BASE +
CTRL_CORE_MMR_LOCK_5,
CTRL_CORE_MMR_LOCK_5_MMR_LOCK_5_TOLOCK);
return;
}
static void APA_UART_DRV_Pinmux_Init(void)
{
uint8_t cnt;
const APA_SOC_MCU_uart_t* pUart = rs_apaSocMcuUart;
for(cnt = 1u; cnt < APA_SOC_MCU_UART_TOTAL; cnt ++)
{
/*Pad configuration and PRCM enable*/
APA_UART_setPinmuxRegs((pUart + cnt)->rxdPadBaseOffset, (pUart + cnt)->rxdMuxVal);
APA_UART_setPinmuxRegs((pUart + cnt)->txdPadBaseOffset, (pUart + cnt)->txdMuxVal);
}
}
static void APA_UART_InstInit(void)
{
ruw_apaSocMcuUartBase = ruw_apaUartBasePtrs[APA_SOC_MCU_UART_INST_1];
}
/*
** A wrapper function performing FIFO configurations.
*/
static void APA_UART_FIFOConfigure(uint32_t base)
{
uint32_t fifoConfig = 0;
/* Setting the TX and RX FIFO Trigger levels as 1. No DMA enabled. */
fifoConfig = UART_FIFO_CONFIG(UART_TRIG_LVL_GRANULARITY_1,
UART_TRIG_LVL_GRANULARITY_4,
1,
UART_FCR_RX_TRIG_LVL_60,
1,
1,
UART_DMA_EN_PATH_SCR,
UART_DMA_MODE_0_ENABLE);
/* Configuring the FIFO settings. */
UARTFIFOConfig(base, fifoConfig);
}
/*
** A wrapper function performing Baud Rate settings.
*/
static void APA_UART_BaudRateSet(uint32_t base)
{
uint32_t divisorValue = 0;
/* Computing the Divisor Value. */
divisorValue = UARTDivisorValCompute(APA_SOC_MCU_UART_MODULE_CLK,
APA_SOC_MCU_UART_BR_230400,
UART16x_OPER_MODE,
UART_MIR_OVERSAMPLING_RATE_42);
/* Programming the Divisor Latches. */
UARTDivisorLatchWrite(base, divisorValue);
}
/*
** A wrapper function performing Interrupt configurations.
*/
static void APA_UART_IntEnable(uint32_t base)
{
/* Configuring INTC to receive UART interrupts. */
APA_UART_INTCConfig();
/* Enabling the specified UART interrupts. */
UARTIntEnable(base, UART_INT_RHR_CTI);
}
/*
** This function configures the INTC to receive UART interrupts.
*/
static void APA_UART_INTCConfig(void)
{
#if 0
/* Crossbar registers are already unlocked, so connect directly */
CSL_xbarIrqConfigure(XBAR_CPU,XBAR_INST,XBAR_INTR_SOURCE);
/* Initializing the Interrupt Controller. */
Intc_Init();
/* Enable the interrupt */
Intc_IntEnable(0);
/* Registering the Interrupt Service Routine(ISR). */
Intc_IntRegister(UART_INT_ID, (IntrFuncPtr) APA_UART_Isr, NULL);
/* Setting the priority for the UART interrupt in INTC. */
Intc_IntPrioritySet(UART_INT_ID, 1, 0);
/* Enabling the UART interrupt in INTC. */
Intc_SystemEnable(UART_INT_ID);
#else
UInt32 cookie = 0;
Vps_printf(" UTILS: IntXbar_connectIRQT !!!\n");
//IntXbar_connectIRQ(UART5_INTR_NUM, XBAR_INTR_SOURCE);
IntXbar_connectIRQ(UART2_INTR_NUM, UART2_INTR_SRC);
//BspOsal_irqXbarConnect(UART5_INTR_NUM, CSL_XBAR_UART5_IRQ);
//BspOsal_irqXbarConnectIrq(UART5_INTR_NUM, UART5_INTR_SRC);
/* Disabling the global interrupts */
cookie = Hwi_disable();
Vps_printf(" UTILS: UART2 INTERRUPT: HWI Create for INT%d !!!\n", UART2_INTR_NUM);
gUtils_tempHwiHandle = BspOsal_registerIntr(UART2_INTR_NUM,
(BspOsal_IntrFuncPtr)APA_UART_Isr,
NULL
);
if( gUtils_tempHwiHandle == NULL)
{
Vps_printf(" UTILS: UART2 INTERRUPT: HWI Create Failed !!!\n");
UTILS_assert(0);
}
Vps_printf(" UTILS: Hwi_enableInterrupt !!!\n");
/* Enable the interrupt */
Hwi_enableInterrupt(UART2_INTR_NUM);
Vps_printf(" UTILS: Hwi_restore !!!\n");
/* Restore interrupts */
Hwi_restore(cookie);
#endif
}
void APA_UART_Init(void)
{
APA_UART_InstInit();
//APA_UART_DRV_Pinmux_Init();
/* Performing a module reset. */
UARTModuleReset(ruw_apaSocMcuUartBase);
/* Performing FIFO configurations. */
APA_UART_FIFOConfigure(ruw_apaSocMcuUartBase);
/* Performing Baud Rate settings. */
APA_UART_BaudRateSet(ruw_apaSocMcuUartBase);
/* Switching to Configuration Mode B. */
UARTRegConfigModeEnable(ruw_apaSocMcuUartBase, UART_REG_CONFIG_MODE_B);
/* Programming the Line Characteristics. */
UARTLineCharacConfig(ruw_apaSocMcuUartBase,
(UART_FRAME_WORD_LENGTH_8 | UART_FRAME_NUM_STB_1),
UART_PARITY_NONE);
/* Disabling write access to Divisor Latches. */
UARTDivisorLatchDisable(ruw_apaSocMcuUartBase);
/* Disabling Break Control. */
UARTBreakCtl(ruw_apaSocMcuUartBase, UART_BREAK_COND_DISABLE);
/* Switching to UART16x operating mode. */
UARTOperatingModeSelect(ruw_apaSocMcuUartBase, UART16x_OPER_MODE);
/* Performing Interrupt configurations. */
APA_UART_IntEnable(ruw_apaSocMcuUartBase);
}
void IntDisable(void)
{
/* Clear GIE */
asm (" CPSID I");
}
void IntEnable(uint32_t status)
{
asm (" CPSIE I");
}
But after I disabled m4 uart2 driver and enable it on A15 dts file:
// DISABLE_COMPLETE(uart2);
uart2: serial@4806c000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806c000 0x100>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
clock-frequency = <48000000>;
status = "disabled";
dmas = <&edma_xbar 51 0>, <&edma_xbar 52 0>;
dma-names = "", "";
};
&uart2 {
status = "okay";
};
dmesg shows below:
[ 1.698409] 4806c000.serial: ttyS1 at MMIO 0x4806c000 (irq = 302, base_baud = 3000000) is a 8250
So I think the driver is loaded. But when I use code which is tested ok before, to receive data, it always timeout.
I checked register "0x4806C000"(UART_RHR), it aways 0. So I think it never received on phy layer.
Since my m4 uart2 driver didn't use dma, so I disable dma in dts, still not work.
I attach A15 driver configured register dump below:
root@dra7xx-evm:~# devmem2 0x4806C000 /dev/mem opened. Memory mapped at address 0xb6f7b000. Read at address 0x4806C000 (0xb6f7b000): 0x00000000 root@dra7xx-evm:~# devmem2 0x4806C004 /dev/mem opened. Memory mapped at address 0xb6fd9000. Read at address 0x4806C004 (0xb6fd9004): 0x00000005 root@dra7xx-evm:~# devmem2 0x4806C008 /dev/mem opened. Memory mapped at address 0xb6fc4000. Read at address 0x4806C008 (0xb6fc4008): 0x000000C1 root@dra7xx-evm:~# devmem2 0x4806C00c /dev/mem opened. Memory mapped at address 0xb6fde000. Read at address 0x4806C00C (0xb6fde00c): 0x00000013 root@dra7xx-evm:~# devmem2 0x4806C010 /dev/mem opened. Memory mapped at address 0xb6f47000. Read at address 0x4806C010 (0xb6f47010): 0x00000003 root@dra7xx-evm:~# devmem2 0x4806C014 /dev/mem opened. Memory mapped at address 0xb6f34000. Read at address 0x4806C014 (0xb6f34014): 0x00000060 root@dra7xx-evm:~# devmem2 0x4806C018 /dev/mem opened. Memory mapped at address 0xb6f85000. Read at address 0x4806C018 (0xb6f85018): 0x00000020 root@dra7xx-evm:~# devmem2 0x4806C01c /dev/mem opened. Memory mapped at address 0xb6fb4000. Read at address 0x4806C01C (0xb6fb401c): 0x00000000 root@dra7xx-evm:~# devmem2 0x4806C020 /dev/mem opened. Memory mapped at address 0xb6f93000. Read at address 0x4806C020 (0xb6f93020): 0x00000000 root@dra7xx-evm:~# devmem2 0x4806C024 /dev/mem opened. Memory mapped at address 0xb6f06000. Read at address 0x4806C024 (0xb6f06024): 0x00000000 root@dra7xx-evm:~# devmem2 0x4806C028 /dev/mem opened. Memory mapped at address 0xb6f2f000. Read at address 0x4806C028 (0xb6f2f028): 0x00000000 root@dra7xx-evm:~# devmem2 0x4806C02c /dev/mem opened. Memory mapped at address 0xb6f4e000. Read at address 0x4806C02C (0xb6f4e02c): 0x00000000 root@dra7xx-evm:~# devmem2 0x4806C030 /dev/mem opened. Memory mapped at address 0xb6eff000. Read at address 0x4806C030 (0xb6eff030): 0x00000042 root@dra7xx-evm:~# devmem2 0x4806C034 /dev/mem opened. Memory mapped at address 0xb6ff7000. Read at address 0x4806C034 (0xb6ff7034): 0x00000007 root@dra7xx-evm:~# devmem2 0x4806C038 /dev/mem opened. Memory mapped at address 0xb6f7a000. Read at address 0x4806C038 (0xb6f7a038): 0x00000040 root@dra7xx-evm:~# devmem2 0x4806C03c /dev/mem opened. Memory mapped at address 0xb6fe5000. Read at address 0x4806C03C (0xb6fe503c): 0x00000000 root@dra7xx-evm:~# devmem2 0x4806C040 /dev/mem opened. Memory mapped at address 0xb6fef000. Read at address 0x4806C040 (0xb6fef040): 0x000000C9 root@dra7xx-evm:~# devmem2 0x4806C044 /dev/mem opened. Memory mapped at address 0xb6fa3000. Read at address 0x4806C044 (0xb6fa3044): 0x00000004 root@dra7xx-evm:~# devmem2 0x4806C048 /dev/mem opened. Memory mapped at address 0xb6f48000. Read at address 0x4806C048 (0xb6f48048): 0x00000000 root@dra7xx-evm:~# devmem2 0x4806C050 /dev/mem opened. Memory mapped at address 0xb6fd6000. Read at address 0x4806C050 (0xb6fd6050): 0x50412E03 root@dra7xx-evm:~# devmem2 0x4806C054 /dev/mem opened. Memory mapped at address 0xb6f42000. Read at address 0x4806C054 (0xb6f42054): 0x0000000D root@dra7xx-evm:~# devmem2 0x4806C058 /dev/mem opened. Memory mapped at address 0xb6f6b000. Read at address 0x4806C058 (0xb6f6b058): 0x00000001 root@dra7xx-evm:~# devmem2 0x4806C05c /dev/mem opened. Memory mapped at address 0xb6f40000. Read at address 0x4806C05C (0xb6f4005c): 0x000000FF root@dra7xx-evm:~# devmem2 0x4806C060 /dev/mem opened. Memory mapped at address 0xb6f77000. Read at address 0x4806C060 (0xb6f77060): 0x00000069 root@dra7xx-evm:~# devmem2 0x4806C064 /dev/mem opened. Memory mapped at address 0xb6f0b000. Read at address 0x4806C064 (0xb6f0b064): 0x00000000 root@dra7xx-evm:~# devmem2 0x4806C068 /dev/mem opened. Memory mapped at address 0xb6f1c000. Read at address 0x4806C068 (0xb6f1c068): 0x00000000 root@dra7xx-evm:~# devmem2 0x4806C06c /dev/mem opened. Memory mapped at address 0xb6fb0000. Read at address 0x4806C06C (0xb6fb006c): 0x00000000 root@dra7xx-evm:~# devmem2 0x4806C070 /dev/mem opened. Memory mapped at address 0xb6feb000. Read at address 0x4806C070 (0xb6feb070): 0x00000003 root@dra7xx-evm:~# devmem2 0x4806C074 /dev/mem opened. Memory mapped at address 0xb6fa3000. Read at address 0x4806C074 (0xb6fa3074): 0x0000001A root@dra7xx-evm:~# devmem2 0x4806C080 /dev/mem opened. Memory mapped at address 0xb6f22000. Read at address 0x4806C080 (0xb6f22080): 0x00000000 root@dra7xx-evm:~# devmem2 0x4806C084 /dev/mem opened. Memory mapped at address 0xb6f26000. Read at address 0x4806C084 (0xb6f26084): 0x00000000
Would you please tell me what I missed? Thanks!
