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AM3352: EMIF timing settings

UNA
Mastermind 7980 points

Part Number: AM3352

Hi,

I have qestions about DDR controller for AM335x. I use SDRAM (DDR3: 800MHz).


Q1: I think the DQS signal needs to be shifted because the DQS and DQ signals are in the same phase at the read timing.
I believe this DQS signal shift is done by the value of RD_DQS_SLAVE_RATIO_CS0, is that correct?

Q2: Is it correct to think that the meaning of RD_DQS_SLAVE_RATIO_CS0 value is the delay time, which is the value of 256 divisions of the period of DDR_CK?

Q3: What is the reason why the reset value of RD_DQS_SLAVE_RATIO_CS0 is 0x40?

Q4: Please tell me about the structure and operation of the master and slave DLLs here.

Q5: Can I assume that the minimum setup time and maximum hold time for the memory controller side (EMIF) are the same as the DDR memory specifications?
　 Setup time: 75 ps(MIN)
     Hold time: 100 ps(max)

Best Regards,
H.U

  • 0
    TI__Guru* 91215 points

    H.U., yes the RD_DQS_SLAVE_RATIO is the amount of 1/256 clocks the DQS signal is shifted.  We use a value of 0x40 (this represents a 1/4 clock cycle) because the memory will launch DQ and DQS at the same time, and the PHY will shift DQS by a quarter cycle to center align DQS with DQ.  The controller will conform to JEDEC specs, so setup/hold will be the same.

    Note that on AM335x, max DDR3 frequency is 400MHz (800MTs), not 800MHz as you state.

    Please use the AM335 EMIF Tool app note https://www.ti.com/lit/pdf/sprack4 to properly configure the AM335x EMIF. 

    Regards,

    James